FPGA VGA + PLL + IP core notes

1. To achieve the intended function! The whole project, do not use routines 25MHZ, all unified use 50MHZ.
2. Use the resolution 800 * 600 @ 72HZ.
3. To achieve a white display only part of the black part RGB == 0, the background color to be displayed.
VGA graphics basics, key parameters:

 

 

 

 

 

 

 

Establish engineering steps
ISE Open
establish PLL IP core.
tool ----> core Generator ----> lower left corner of the input clock ---- "menu bar new construction ----" clock wizard ----> input 50MHZ, output 25MZH ---- "return project add source ---> Add **. xco, and a **. v.
Add a constraint:
project right new source ---> Implentation constrains file ---- > click on the menu bar on the right bulb ---- "ucf ----> FPGA ----> io ----> SINGLE ended ----> spantan 6 -> input attribbute ----> copy the ucf file
edit ucf file
to see the schematic view the introduction of IO number, written on the voltage level
add chipscope oscilloscope, right-engineering new source --- omitted. After you create a project can be seen in the following * .cdc file, double-click the setting parameters logic analyzer.
Note:
The following diagram must click inside the menu, otherwise the timing wrong, the role of the bit file down into the board!

 

 

 

I monitor does not support routine resolution, instead 800 * 600 @ 72HZ. Parameters are as follows:

 

 

从上图看出，行列扫码总像素是1040*666pixel。
VGA动态移动图形
关键在于思路，只要做好移动变量x,y的增加，减少，以及这两个方向的flag，就可以完美控制方框的移动了！
最终实现了图形移动显示。