1. Engineering organization form
The organization of the project generally includes the following parts, which are doc, par, rtl and sim. doc: generally store project-related documents, including datasheet (data manual), design plan, etc. used in the project. However, in order to make it easier for everyone to view, our development board documents are collected and stored under the data disk;
par: Mainly store project files and some IP files used;
rtl: It mainly stores the RTL code of the project. This is the core of the project. The file name and the module name should be consistent. It is recommended to store them separately according to the module level;
sim: It mainly stores the simulation code of the project. In complex projects, simulation is also an indispensable part, which can greatly reduce the workload of debugging.
2.
File header declaration
At the beginning of every Verilog file, there must be a statement. Including the copyright, author, creation date and content introduction of the file, as shown in the following table.
3. Input and output definition
① a row defines only a signal;
② All signals are aligned;
③ Put the signals of the same group together.
4.
Parameter
definition
①
The parameter declaration in the
module
is
not recommended to be placed everywhere;
② Put the
parameter
definition immediately
after the input and output definition of the
module
;
③
All names of constants such as
parameters
are capitalized.
5.
Wire/reg
definition
① Put
the definition of
reg
and
wire
immediately after
parameter
;
② It is recommended that the signals with the same function are put together;
③ The signal needs to be aligned, the
reg
and bit width need to be empty by
2
spaces
, and the bit width and signal name must be empty by at least four spaces;
④ The bit width is described in descending order,
[6:0]
;
⑤ The clock uses the prefix
clk
, and the reset uses the suffix
rst
;
⑥
Verilog
keywords cannot be used
as signal names;
⑦ Only one signal is defined in a line.
6 . Signal name
① Signal naming needs to reflect its meaning, for example,
fifo_wr
represents
FIFO
read and write enable;
② You can use "_" to separate signals, such as sys_clk
;
③ Do not use uppercase or mixed case for internal signals. It is recommended to use all lowercase;
④ Use lowercase for the module name;
⑤ For low-level active signals, use
_n
as the signal suffix;
⑥ Asynchronous signal, use
_a
as the signal suffix;
⑦ Pure delayed beat signal uses
_dly
as the suffix.
7.
Always
block description
①
If
needs four blanks;
② An always
needs a begin
and
end
;
③
A comment is required in front of
always
;
④
Beign
suggests to
put it on the same line as
always
;
⑤ One always
and the next always need to be
blank one line, don’t blank multiple lines;
⑥ The clock reset trigger description uses
posedge sys_clk
and
negedge sys_rst_n
⑦ An always
block contains only one clock and reset;
⑧ The sequential logic uses non-blocking assignment.
8. Assign block description method
①
The logic of
assign
cannot be too complicated, otherwise the legibility is not good;
②
A comment is required before
assign
;
③ Combinatorial logic uses blocking assignment.
9.
Spaces and
TAB
Because different interpreters are inconsistent with TAB translation, it is recommended not to use TAB and use all spaces.
10.
Comments
① The comment description needs to be clear and concise;
② Do not use nonsense and redundant descriptions;
③ The comment description needs to use "//";
④ The comment description needs to be aligned;
⑤ Notes need to be added between core code and signal definition.
11.
Module instantiation
① The
moudle
module instantiation is represented by
u_xx
.
12. Other
① The simpler the code, the better, so that it is easy for others to read and understand;
② Do not use
loop statements such as
repeat
;
③ The
initial statement is not used in
RTL
code
, except for simulation code;
④ Avoid generating
Latch
latches, such as
if
there is
no
else
branch in
combinatorial logic , and the
case
lacks a
default
statement;
⑤ Avoid using too complicated and rare grammar, which may result in lower optimization of the grammar synthesizer.
Good coding style is my insistence!
