FPGA study notes
Quartus II prime Standard Edition—calling memory IP core
The calling method of the old version of Quartus II and the new version of the IP core is somewhat different. The following is the calling method of the Quartus II prime Standard Edition, for reference only.
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As shown in the figure below, click IP Catalog in assignmen, enter ram, and double-click RAM:2-PORT
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Select the storage size of the port information memory according to your needs, click next
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Select the data width according to your needs, click next
- Auto: Automatically allocate
LCs: internal register
M9K: internal block ram
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Select the clock type, click next
Creat byte enable for port A: For the situation when the bit width is greater than 8 bits -
Select the port registration method, click next
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Select the memory initialization content, click next
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Click next
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Click Finish to call the ram ip core to complete.
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Right-click the project file, and add the called ram .v file to the project in sequence 1, 2, 3
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After adding, perform simulation verification function
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Create testbench for simulation verification
//----testbench-------------------------------------
`timescale 1ns/1ns
`define clock_period 20
module ram_dual_tb;//ram_dual
reg clk;
reg [7:0] data;
reg [7:0] rdaddress;
reg [7:0] wraddress;
reg wren;
wire [7:0] q;
integer i;
//----例化ip核---------------------------------
ip ram_dual(
.clock(clk),
.data(data),
.rdaddress(rdaddress),
.wraddress(wraddress),
.wren(wren),
.q(q)
);
//----激励设置--------------------------------
initial clk = 1;
always begin #(`clock_period/2) clk = ~clk;end
initial begin
data = 0;
rdaddress = 32;
wraddress = 0;
wren = 0;
#(`clock_period*30+1);
for(i=0;i<=15;i=i+1)begin
wren = 1;
data = 255-i;
wraddress = i;
#(`clock_period);
end
wren = 0;
#(`clock_period*30+1);
for(i=0;i<=15;i=i+1)begin
rdaddress = i;
#(`clock_period);
end
#(`clock_period*30);
$stop;
end
endmodule
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~