Table of contents
What are the forms of existence of IP core? What are the pros and cons of each?
What are the disadvantages of IP core?
How to call IP core in Quartus II?
Basic working principle of PLL
Setting of PPL Phase Locked Loop IP Core
Setting interface: the first section
Setting interface: the second section
foreword
What is an IP core?
Answer: IP core is a module used in the field of "ASIC" and "FPGA", a circuit with pre-designed functions.
For example, "FIFO", "RAM", and "SDRAM controller" in digital circuits are commonly used and complex functional modules with adjustable parameters.
Why use IP core?
Answer: Because a pre-designed adjustable function module can save development time.
What are the forms of existence of IP core? What are the pros and cons of each?
Answer: soft core --> corresponding language form: HDL language form; (does not involve physics, but not very safe)
Solid core --> netlist form, such as PCIE; (specific signals can be pre-wired, but may affect the layout of other circuits)
Hard core --> layout form; (complete netlist wiring and strong security, but inflexible and inconvenient to transplant)
What are the disadvantages of IP core?
Answer: It is difficult to use across platforms; the core code cannot be seen; custom IP requires additional fees.
Call of IP core in Quartus II
(Common) Mega Wizard plug-in manager; SOPC constructor; DSP constructor; Qsys design system instantiation.
How to call IP core in Quartus II?
Step 1: Click to enter the IP core call
Step 2: Create a new IP core
Step 3: Select the desired IP core and the corresponding settings of the IP core (here take PLL as an example)
Corresponding chip model, language, and storage address
Step 4: Successfully enable IP, adjust parameters
Tabs indicate:
1. About: You can view the basic information of the IP core, such as supporting chips, etc.;
2. Documentation: The IP core document is easy to understand in depth;
3. The third tab is used for: parameter adjustment (the sub-tabs are: overall/mode, output/lock);
4. The fourth tab is used to: reconfigure attributes, such as storing address chips, etc.;
5. The fifth tab is used to: configure the output clock;
6. Tab No. 6 is used for: EDA configuration;
7. The seventh tab is used for: overall configuration.
(Note: The detailed explanation is in-> Station B--[Wildfire] FPGA series teaching video--43-Lecture 25--4 minutes and 30 seconds)
IP core: PLL
Introduction
PLL, also known as phase-locked loop, is one of the most commonly used phase-locked loops. He can perform arbitrary frequency division, frequency multiplication, phase adjustment, and duty cycle adjustment on the FPGA clock signal.
Extension: PLL can be classified as a digital phase-locked loop. Digital phase-locked loops are controllable and adjustable.
Basic working principle of PLL
multiplier
frequency division
Setting of PPL Phase Locked Loop IP Core
Setting interface: the first section
General/Mode main content: mode setting (normal mode is generally used)
general pattern
Zero Delay Buffer Mode
Source synchronous mode (generally used for data interfaces (especially high speed))
no compensation mode
Input/Lock main content:
Clock switchoven main content: (generally no modification)
