The validity of data
Data on the SDA line must be stable at the high level period of the clock. High or low state of the data line can only change when the clock signal on the SCL line is low.
Start and stop conditions
SCL line is high level, the SDA line is switched from the high level to the low level, this situation represents a starting condition;
SCL line is high level, the SDA line is switched from the low level to the high level, this situation represents a stopping condition
START and STOP conditions typically generated by the host, after a start condition that the bus is busy
I2C bus data transfer
Sent to the SDA line must be 8 bits per byte, number of bytes that can be transmitted per transfer is not limited. After each byte must be followed by an acknowledge bit. First, the transmission data is the most significant bit (the MSB), if complete confidential from other functions (e.g., an interrupt service routine) to receive or transmit at a full data bytes, may be held low clock line SCL , forcing the master into a wait state, when the slave is ready to receive the next byte of data and releases the data transfer clock line SCL to continue .
