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Serial and Parallel Communication
Introduction to SPI Communication
Advantages and disadvantages of SPI
SPI bus protocol overview
SPI is a common communication protocol used by many different devices. For example, SD card reader modules, RFID card reader modules, and 2.4GHz wireless transmitter/receivers all use SPI to communicate with microcontrollers.
Communication between electronic devices is like communication between people. Both parties need to speak the same language. In electronics, these languages are called communication protocols. Common communication protocols are SPI, UART, I2C, etc.
First, we will start with some basic concepts about electronic communication and then explain in detail how SPI works.
SPI, I2C and UART are much slower than protocols like USB, Ethernet, Bluetooth and WiFi, but they are simpler and use less hardware and system resources. SPI, I2C, and UART are ideal for communication between microcontrollers and between microcontrollers and sensors that do not need to transfer large amounts of high-speed data.
Serial and Parallel Communication
Electronic devices communicate with each other by sending bits of data over the wires that physically connect the devices. Devices communicate by passing bits, which are binary and can only be 1 or 0. Bits are transferred from one device to another through rapid changes in voltage. In a 5 V operating system, 0V has a voltage value of 0, and 5V has a voltage value of 1.
Data bits can be transferred in parallel or serially. In parallel communication, data bits are sent simultaneously, and each data bit is sent over a separate wire. The following diagram shows the parallel transmission of the letter "C" in binary (01000011):
In serial communication, bits are sent one by one over a single wire. The following diagram shows the serial transmission of the letter "C" in binary (01000011):
Introduction to SPI Communication
A unique advantage of SPI is that data can be transferred without interruption. Any number of bits can be sent or received in a continuous stream. With I2C and UART, data is sent in packets, limited to a specific number of bits. The start and stop conditions define the start and end of each packet, so data is interrupted during transmission.
Devices that communicate via SPI are in a master-slave relationship. The master is the controlling device (usually a microcontroller), and the slaves (usually a sensor, display, or memory chip) get instructions from the master. The simplest configuration of SPI is a single master, single slave system, but one master can control multiple slaves (more on this below).
MOSI (Master Out/Slave In) : The line on which the master sends data to the slave.
MISO (Master Input/Slave Output) : The line on which the slave sends data to the master.
SCLK (clock) : The line for the clock signal.
SS/CS (Slave Select/Chip Select) : Master select line used to select which slave to send data to.
| required line |
2 |
| maximum rate |
up to 10Mbps |
| synchronous or asynchronous |
Synchronize |
| serial or parallel |
serial |
| Maximum number of hosts |
1 |
| Maximum number of slaves |
theoretically unlimited |
In practice, the number of slaves is limited by the system load capacitance, which reduces the ability of the master to precisely switch voltage levels.
How SPI works
clock
The clock signal synchronizes the master's data bit output with the slave's bit sampling. One bit of data is transferred per clock cycle, so the speed of data transfer is determined by the frequency of the clock signal. SPI communication is always initiated by the master because the master configures and generates the clock signal.
Any communication protocol in which devices share a clock signal is called synchronization. SPI is a synchronous communication protocol. There are also asynchronous methods that do not use a clock signal. For example, in UART communication, both sides are set to a pre-configured baud rate, which determines the speed and time of data transfer.
Clock signals in SPI can be modified using the clock polarity and clock phase properties. These two properties work together to define when bits are output and when bits are sampled. Clock polarity can be set by the master to allow bits to be output and sampled on the rising or falling edge of the clock cycle. The clock phase can be set to output and sample on the first or second edge of the clock cycle, whether it is rising or falling.
In SPI, the master can choose the clock polarity and clock phase. The CPOL bits set the polarity of the clock signal during the idle state. The idle state is defined as the period when CS is high and transitions low at the beginning of the transfer, and the period when CS is low and transitions high at the end of the transfer. The CPHA bits select the clock phase. Depending on the CPHA bit, a rising or falling clock edge is used to sample and/or shift data. The master must select the clock polarity and clock phase according to the requirements of the slave. Four SPI modes are available depending on the CPOL and CPHA bit selection. The four SPI modes are shown in the table.
| SPI mode |
CPOL |
CPHA |
Clock Polarity in Idle State |
Clock phase for sampling and/or shifting data |
| 0 |
0 |
0 |
logic low |
Data is sampled on the rising edge and shifted out on the falling edge |
| 1 |
0 |
1 |
logic low |
Data is sampled on the falling edge and shifted out on the rising edge |
| 2 |
1 |
0 |
logic high |
Data is sampled on the rising edge and shifted out on the falling edge |
| 3 |
1 |
1 |
logic high |
Data is sampled on the falling edge and shifted out on the rising edge |
The following figures show examples of communication in the four modes of the SPI, where data is displayed on the MOSI and MISO lines. The start and end of the transfer are represented by dashed green, sampling edges in orange, and shifting edges in blue.
Mode 0
In this mode, the clock polarity is 0, indicating that the idle state of the clock signal is low. The clock phase in this mode is 0, meaning that data is sampled on the rising edge (shown by the orange dotted line) and data is shifted on the rising edge of the clock signal (shown by the blue dotted line).
Mode 1
In this mode, the clock polarity is 0, indicating that the idle state of the clock signal is low. The clock phase in this mode is 1, meaning that data is sampled on the falling edge (shown by the orange dotted line) and data is shifted on the falling edge of the clock signal (shown by the blue dotted line).
Mode 2
In this mode, the clock polarity is 0, indicating that the idle state of the clock signal is low. The clock phase in this mode is 1, meaning that data is sampled on the falling edge (shown by the orange dotted line) and data is shifted on the rising edge of the clock signal (shown by the blue dotted line).
Mode 3
In this mode, the clock polarity is 0, indicating that the idle state of the clock signal is low. The clock phase in this mode is 1, meaning that data is sampled on the falling edge (shown by the orange dotted line) and data is shifted on the rising edge of the clock signal (shown by the blue dotted line).
Dependent selection
A master can select a slave to communicate with by setting the slave's CS/SS line low. In the idle, non-transmitting state, the slave select line remains high. There may be multiple CS/SS pins on the master, allowing multiple slaves to be wired in parallel. If there is only one CS/SS pin, multiple slaves can be daisy-chained to the master.
multiple slaves
normal method
The SPI can be set up to work with a single master and a single slave, or multiple slaves controlled by a single master. There are two ways to connect multiple slaves to the master. If the master has multiple slave select pins, the slaves can be paralleled as follows:
In regular mode, a single chip needs to be selected from the master for each slave. Once the chip select signal is enabled (pulled low) by the master, the clock and data on the MOSI/MISO lines are available for the selected child node. If multiple chip select signals are enabled, the data on the MISO line will be corrupted because the master node cannot identify which child node is transmitting data.
As can be seen from the figure, as the number of child nodes increases, so does the number of lines that the chip selects from the master node. This can quickly increase the number of inputs and outputs required by the master and limit the number of slaves that can be used. There are different techniques that can be used to increase the number of slaves in regular mode; for example, using a multiplexer to generate chip select signals.
Daisy Chain Method
If only one slave select pin is available, the slaves can be daisy-chained as follows:
In daisy-chain mode, the slaves are configured such that the chip select signals of all slaves are tied together and data is propagated from one slave to the next. In this configuration, all subnode slaves receive the same SPI clock. Data from the master goes directly to the first slave, which feeds data to the next slave, and so on.
In this method, as data propagates from one slave to the next, the number of clock cycles required to transfer the data is proportional to the position of the slaves in the daisy chain. For example, in the figure, in an 8-bit system, it takes 24 clock pulses to use the data on 3. And the third slave only has 8 clock pulses in regular SPI mode. The figure shows the clock cycles and data propagating through the daisy chain. Not all SPI devices support daisy-chain mode.
MOSI sum MISO
The master sends data to the slave serially bit by bit over the MOSI line. The slave receives data sent from the master on the MOSI pin. Data sent from master to slave is usually sent with the most significant bit first .
The slave can also send data back to the master serially over the MISO line. Data sent from the slave back to the master is usually sent with the least significant bit first .
Steps of SPI Data Transfer
1. The host outputs the clock signal:
2. The master switches the SS/CS pin to a low state to activate the slave:
3. The master sends data to the slave one bit at a time along the MOSI line. The slave reads the received bit: the high bit is read first
4. If a response is required, the slave returns the data to the master one bit at a time along the MISO line. The host reads when the reception is in place: the low bit is read first
Advantages and disadvantages of SPI
There are advantages and disadvantages to using SPI, to choose between different communication protocols, you should know when to use SPI based on your project requirements:
advantage
- No start and stop bits, so data can be streamed continuously without interruption
- No complex slave address system like I2C
- Data transfer rate higher than I2C (almost twice as fast as I2C)
- Separate MISO and MOSI lines so data can be sent and received simultaneously
shortcoming
- Use four wires (I2C and UART use two wires)
- There is no verification that the data was successfully received (I2C has this value)
- No form of error checking like parity bits in UART
- Only allow a single host
Summary of common buses
[Bus] One article to understand the UART communication protocol
[Bus] One article to understand the I2C communication protocol