Today, I spent half a day learning the I2C bus protocol, which is quite thorough. I took it out and shared it with you.
·I2C bus features
Three states of I2C bus
·I2C bus necessary knowledge points
·I2C bus write process
·I2C bus read process
1. Characteristics of I2C bus
Before speaking, I drew a picture for you.
Judging from the picture, it is relatively simple, but although the sparrow is small and complete, everything it wants to express can be seen in the picture.
From the figure we can see that the characteristics of the I2C bus are:
1. It is composed of two lines, one is called SCL (serial clock line) and the other is called SDA (serial data line). There are few lines, so there is no need to say more about the benefits, but the speed is definitely slow, and it is enough to be used as a data interface between peripherals. The fast internal communication of the chip uses the AMBA bus communication. If you want to know more, you can check it yourself, or I will write it after a few days of research.
2. Each I2C chip can be used as a master and a slave, but only one master is allowed in one pass.
Aren't the two characteristics a little bit lacking? It's fine. After understanding the following knowledge points, let's summarize it yourself, and mainly talk about the latter content.
Second, the three states of the I2C bus
There are three states of the I2C bus:
1. Idle
2. The work begins
3. Work stops
Let's talk about the idle state first: when SCL and SDA are high at the same time, it is idle state. To put it bluntly, it does nothing. As shown below:
Let's talk about the start working state. At this time, SCL is high, and SDA has a falling edge, as shown in the following figure:
The last is to stop working. At this time, SCL is high and SDA has a rising edge, as shown in the following figure:
3. Necessary knowledge points of I2C bus
In addition to knowing the above three states, you also need to know the following five points before you can understand the final reading and writing process. Coming soon, pick up:
1. The I2C bus protocol requires a byte width of 8 bits (8bit)
2. The bit width of the slave address is 7 bits, but as mentioned above, a byte needs 8 bits, don’t worry, there is also a bit width of 1 bit to store whether the host is used to write (0) or read (1). ), which adds up to exactly 8 bits. For example , 0100101 (address bit) 0 (read-write bit, here is write), it can be seen that the read-write bit is the lowest bit.
3. Each I2C chip has its own address, which may be the same or different from each other. At the same time, it is to realize data exchange between one master and multiple slaves at the same time. In order to make each I2C chip more flexible, each I2C chip has a fixed 4-bit address and a 3-bit programmable address. When the 4-bit fixed address is the same, use software to edit the last 3 bits to make them the same, so at most There can be 8 (cubic of 2) slaves that can communicate with the master at the same time.
4. After a byte is transmitted, the host will pull SDA high, the host I2C chip will no longer work, waiting for the slave feedback (ACK acknowledge), then the slave I2C chip will start to judge the transmission process and read On success, pull SDA low to signal I'm done, you go ahead. After the host gets this message, it will perform the next predetermined operation. If the slave read fails, then SDA will not change. At this point, the host will know, oh, it didn't send successfully, the next step is to continue to retransmit or terminate the operation, which is determined by the written program. At this point, do you think that there will be a bug, that is, as long as the SDA remains unchanged, the host will not work all the time? Of course, the host is not a fool (in fact, it should be a programmer and not a fool), so wait for a while. If I can't receive the signal and pull it down within a certain period of time, I think you have a problem. This time is half the SCL cycle.
5. The clock cycle is mentioned in 4, here is more popular science. Look at the picture below (download, and Baidu watermark):
As can be seen from this figure, a whole process should be 9 clock cycles, and in the high process of the ninth cycle, ACK must be completed. Each bit of data corresponds to a high. During this half cycle, the data on SDA is required to be stable and cannot be changed. Why? It is understood in terms of hold time like setup time.
Fourth, the I2C bus writing process
The writing process is as follows:
1. The master sends the slave address (7bit)+0 (0 is write), all slaves will receive this information, but only the slaves with matching addresses feed back an ACK (0), and prepare for the subsequent receiving work, other addresses Wrong slave, 'wash up and sleep early, it's nothing to do with us'.
2. The host receives this ACK and starts to send the memory address (8bit), all slaves whose addresses match (as mentioned earlier, a host can match multiple slaves, as long as the slave addresses are the same) receive the 8bit memory address , after instructing to go down, give the host a feedback ACK (0), 'I am OK'.
3. The master receives this ACK, and starts to send data to the slave, one byte is 8 bits, the slave receives it, and returns ACK (0) to the master.
4. When the host receives this ACK, whether to continue sending data or sending a termination signal depends on whether the data is sent.
Five, I2C bus reading process
The reading process is as follows:
1. The host sends the slave address (7bit) + 0 (0 is write), why is it written here? First of all, the master has to find these slaves, of course, the slave address must be written to each slave. All slaves will receive this information, but only the slaves with matching addresses feed back an ACK (0), and prepare for the subsequent receiving work, other slaves with the wrong address, 'Eh... wash and sleep early , we have nothing to do again'.
2. The master receives this ACK and starts to send the 8bit memory address to the slave, 'Find this address, take out the goods for me and prepare them, I will pick up the goods from you later!'. After the slave finds these addresses, it feeds back an ACK (0) to the master.
3. The host receives the ACK and sends the slave address (7bit) again, but this time the last one is changed to 1 (read). The slave receives and returns ACK(0).
4. The master receives this ACK and is ready to receive the slave information. At this time, the slave information arrives. After the master receives the information, it does not send feedback to the slave (after all, the master is the boss, and the master has to give it to the junior Myself, make a report?) Directly initiate a termination signal and feel distressed for the slave for 3 seconds.
Okay, that's it for now, continue to feel distressed about the slave machine for 3 seconds...