concept
Two-wire serial bus. The serial bus composed of data line SDA and clock SCL can send and receive data. ( Half-duplex communication ) Two-way transmission is performed between the CPU and the controlled IC, and between the IC and the IC. The high-speed IIC bus can generally reach more than 400kbps.
I2C protocol
idle state
When the two signal lines SDA and SCL of the I2C bus are at high level at the same time, it is defined as the idle state of the bus . At this time, the output stage field effect transistors of each device are in the cut-off state, that is, the bus is released, and the level is pulled high by the pull-up resistors of the two signal lines.
start signal and stop signal
- Start signal: When SCL is high , SDA jumps from high to low; the start signal is a level jump timing signal, not a level signal.
- Stop signal: When SCL is high , SDA jumps from low to high; the stop signal is also a level jump timing signal, not a level signal.
How to understand the start signal and stop signal in a popular way?
We can regard SDA as a single-pole single-throw switch. I put the switch down (that is, the process of SDA from high to low), and SDA and SCL are connected , which can be regarded as the beginning (start). On the contrary, I lift the switch (that is, the process of SDA from low to high), SDA and SCL are disconnected , which can be regarded as the end (stop).
Acknowledgment signal ACK
Every time the transmitter sends a byte (8 bits), it releases the data line during the clock pulse 9 , and the receiver feeds back a response signal. When the response signal is at a low level, it is defined as an effective response bit (ACK for short) , indicating that the receiver has successfully accepted the byte (that is, when the eighth signal has been received, that is, a complete reception has been received) byte, it is time to pull down the SDA data line); when the response signal is high, it is specified as a non- acknowledgment bit (NACK) , which generally indicates that the receiver has not successfully received the byte.
The requirement for feeding back the valid acknowledgment bit ACK is that the receiver pulls the SDA line low during the low level period before the ninth clock pulse, and ensures that it is a stable low level during the high level period of the clock.
If the receiver is the master, after it receives the last byte, it sends a NACK signal to inform the controlled transmitter to end the data transmission and release the SDA line so that the master receiver sends a stop signal P.
data validity
When the I2C bus is transmitting data, the data on the data line must remain stable when the clock signal is at a high level. Variations are allowed.
That is: the data needs to be ready before the rising edge of SCL arrives, and must be stable before the falling edge arrives.
data transmission
Each bit of data transmitted on the I2C bus has a corresponding clock pulse (or synchronous control), that is, with the cooperation of the SCL serial clock, each bit of data is serially transmitted bit by bit on the SDA. The transmission of data bits is edge triggered .
IIC read and write process
Write data from master to slave
(Gray means master→slave , white means slave→master ; A means ACK, non-A means NACK, read and write bit: 0 write/1 read)
Process: First, the host will generate a start signal to start data transmission. Then the master sends the address bit and read-write bit 0 to the slave (because it is necessary to determine which slave and what operation to do), after the response is successful, it will start sending data, and the slave will return a valid response or an invalid response according to the received data. Until the host generates a stop signal, it means that the transmission is over.
Read data from master
(Gray means master→slave, white means slave→master; A means ACK, non-A means NACK, read and write bit: 0 write/1 read)
Process: The general logic is the same as above, so I won’t go into details here.
Multi-master IIC bus arbitration
When multiple devices are hung on the IIC bus, sometimes two or more master devices want to occupy the bus at the same time (bus competition). The IIC bus has multi-master capability, so bus arbitration is required at this time .
When multiple master devices want to occupy the bus at the same time, if one master device sends a high level and another master device sends a low level, the device whose sending level does not match the SDA bus level at this time will automatically turn off its output stage .
Arbitration of bus contention is carried out on two levels: First, the comparison of address bits , if the master device addresses the same slave device, then enter into data bit comparison, thus ensuring the reliability of contention arbitration. Because the information on the IIC bus is used for arbitration, no loss of information will be caused .
For example :
Assuming that the data DATA1 to be sent by the master controller 1 is " 101 ...", the data DATA2 to be sent by the master controller 2 is " 1001 ...", after the bus is started, the two master controllers must check each time a data bit is sent. Their own output level is detected. As long as the detected level is consistent with the level sent by themselves, they will continue to occupy the bus. In this case, they still cannot get arbitration. When the master controller 1 sends the third bit of data " 1" (main controller 2 sends "0") , because the result of " wire AND " the level on SDA is "0", so when the main controller 1 detects its own output level, it will detect an AND At this time, the master controller 1 has no choice but to give up control of the bus ; therefore the master controller 2 becomes the sole master of the bus.
it's easy to see:
- During the entire arbitration process, neither master 1 nor master 2 will lose data.
- Individual masters have no priority level of control over the bus.
- The bus control is determined immediately, and they follow the principle of " low level priority ", that is, whoever sends the low level first will take control of the bus.
Summarize:
- The master controller adjusts the speed synchronization problem with the slave device by detecting the level of SCL - clock synchronization.
- The master controller judges whether a bus "conflict" occurs by detecting the level sent by itself on SDA - bus arbitration . Therefore, the "clock synchronization" and "bus arbitration" of the I2C bus are realized by the special structure of the device's own interface.
IIC CubeMX configuration
configuration
1. Set the RCC clock and configure it as a high-speed external clock HSE to select an external clock source
2. IIC configuration
Here is to talk about Clock stretching (clock stretching) : clock stretching suspends a transmission by pulling the SCL line low , and the transmission will not continue until the SCL line is released to a high level . Clock stretching is optional , actually most slave devices don't include SCL drivers, so they can't stretch the clock.
important function
In fact, such as sending interrupts and receiving interrupts are also important, but because the space is too long, I won’t describe them too much. In fact, they are similar to serial port interrupts. Here are some of the most basic communication functions:
HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c,uint16_t DevAddress,uint8_t *pData,uint16_t Size,uint32_t Timeout);
- 功能： 写数据
- 参数：
*hi2c 设置使用的是那个IIC 例：&hi2c1
DevAddress 写入的地址 设置写入数据的地址 例：0xA0
*pData 需要写入的数据
Size 需要发送的字节数
Timeout 最大传输时间，超过传输时间将自动退出传输函数
// 发送两个字节数据，IIC写数据函数
- 例如：HAL_I2C_Master_Transmit(&hi2c1,0xA0,(uint8_t*)TxData,2,1000);
HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c,uint16_t DevAddress,uint8_t *pData,uint16_t Size,uint32_t Timeout);
- 功能： 接收数据
- 参数：
*hi2c 设置使用的是那个IIC 例：&hi2c2
DevAddress 写入的地址 设置写入数据的地址 例：0xA0
*pData 存储读取到的数据
Size 需要发送的字节数
Timeout 最大传输时间，超过传输时间将自动退出传输函数
HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
- 功能：IIC写多个数据，该函数适用于IIC外设里面还有子地址寄存器的地址，比如E2PROM，除了
设备地址，每个存储字节都有其对应的地址。
- 参数：
*hi2c 设置使用的是那个IIC 例：&hi2c2
DevAddress 写入的地址 设置写入数据的地址 例：0xA0
MemAddress 从机寄存器地址，每写入一个字节数据，地址就会自动+1
MemAddSize 从机寄存器地址字节长度 8位/16位
写入数据的字节类型 8位/16位
I2C_MEMADD_SIZE_8BIT
I2C_MEMADD_SIZE_16BIT
*pData 需要写入的数据的起始地址
Size 传输数据的大小，需要发送的字节数
Timeout 最大传输时间，超过传输时间将自动退出传输函数
- 例如：HAL_I2C_Mem_Write(&hi2c1,ADDR,i,I2C_MEMADD_SIZE_8BIT,&(I2C_Buffer_Write[i]),8,1000);
In fact, HAL_I2C_Mem_Write is equivalent to first using HAL_I2C_MHALaster_Transmit to transmit the first register address, and then using HAL_I2C_MHALaster_Transmit to transmit the data written to the first register.
Therefore, if you just read/write data to a certain peripheral , then use Master_Receive/Master_Transmit . If it is a peripheral , there are sub-addresses (like E2PROM), device addresses, and register storage for each data. address, use Mem_Write . (Mem_Write has two addresses, and Master_Transmit has only slave addresses).