Summary:
Xilinx FPGA Platform Ethernet Interface (Summary)
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Second, the MAC layer interface
1. System Architecture
Based on the TOP-DOWN design idea, we first need to understand the system model of FPGA-based Ethernet interface design:
MAC is Media Access Controller. Ethernet MAC is defined by the IEEE-802.3 Ethernet standard. It implements the data link layer. The latest MAC supports 10/100/1000Mbps rate at the same time. Usually, it implements interfaces such as MII/GMII/RGMII to implement interfaces with industry standard PHY devices.
The MAC consists of a hardware controller and a MAC communication protocol. This protocol is located in the lower half of the data link layer in the OSI seven-layer protocol, and is mainly responsible for controlling and connecting the physical medium of the physical layer.
The MAC layer can write its own code or use off-the-shelf IP. Implemented by FPGA.
PHY is a physical layer device in the TCP/IP protocol stack, which is what we often call aPHY chip, such as 88E1111, which supports different forms of data conversion into transmission media supported by Ethernet, such as 1000BASE-T, 100BASE-T, 10BASE-T type Ethernet transmission. Supports data transmission and reception over CAT-5 unshielded twisted pair cables. It can be directly connected to the MAC/SWITCH interface, such as the IP core of the FPGA. Support RMII, GMII, RGMII, SGMII, XAUI and other interfaces.
The role of the PHY chip can be said to be the adaptation between the MAC layer and the twisted pair cable.
RJ45 is a kind of information socket (ie, communication terminal) connector in the wiring system. The connector consists of a plug (connector, crystal head) and a socket (module). The plug has 8 grooves and 8 contacts. RJ is the abbreviation of Registered Jack, which means "registered jack". In FCC (Federal Communications Commission Standards and Regulations), RJ is an interface that describes a public telecommunication network, and RJ45 of a computer network is a common name for a standard 8-bit modular interface. is the connector.
Based on this system architecture, we continue to understand the MAC layer interface.
PS: Insert an OSI seven-layer structure and TCP/IP five-layer structure model
2. MAC layer interface
MII interface : Medium Independent Interface, medium independent interface. Generally used between the MAC layer and the PHY layer of the Ethernet hardware platform, there are many types of MII interfaces, commonly used interfaces such as MII, RMII, GMII, RGMII, SGMII, and XAUI.
MII port:
- RXD(Receive Data)[3:0]: data receiving signal, a total of 4 signal lines;
- TX_ER(Transmit Error): Send data error prompt signal, synchronized with TX_CLK, active high, indicating that the data transmitted within the validity period of TX_ER is invalid. For 10Mbps rate, TX_ER does not work;
- RX_ER (Receive Error): Receive data error prompt signal, synchronized with RX_CLK, active high, indicating that the data transmitted within the validity period of RX_ER is invalid. For 10Mbps rate, RX_ER does not work;
- TX_EN(Transmit Enable): Send enable signal, only the data transmitted within the validity period of TX_EN is valid;
- RX_DV(Reveive Data Valid): Receive data valid signal, the function type is TX_EN of the transmission channel;
- TX_CLK: transmit reference clock, at 100Mbps rate, the clock frequency is 25MHz, at 10Mbps rate, the clock frequency is 2.5MHz. Note that the direction of the TX_CLK clock is from the PHY side to the MAC side, so this clock is provided by the PHY.
- RX_CLK: Receive data reference clock, at 100Mbps rate, the clock frequency is 25MHz, at 10Mbps rate, the clock frequency is 2.5MHz. RX_CLK is also provided by the PHY side.
- CRS: Carrier Sense, carrier detection signal, does not need to be synchronized with the reference clock, as long as there is data transmission, CRS is valid, in addition, CRS is only valid in half-duplex mode of PHY;
- COL: Collision Detectd, collision detection signal, does not need to be synchronized with the reference clock, only the PHY is valid in half-duplex mode.
The interface has a total of 16 wires.
The remaining RMII, GMII, RGMII and other interfaces will not be listed in such detail. We can use a table (from: "Smashing Thoughts") to compare and understand clearly, focusing on the change of speed.
| MII |
Basic 100Mbps/10Mbps interface |
RXD[3:0]、TXD[3:0] TX_ER 、 TX_EN RX_ER 、 RX_DV TX_CLK、RX_CLK CRS、COL |
Clock=25MHz or 2.5MHz Data bit width 4bit (4bit data is transmitted in one clock cycle) 100Mbps=25 MHz *4bit 10Mbps=2.5 MHz *4bit |
| RMII |
100Mbps/10Mbps interface simplified on the basis of MII; Maintain the same rate as MII by increasing the Clock frequency; |
RXD[1:0]、TXD[1:0] TX_EN RX_ER CLK_REF CRS_DV |
Clock=50MHz Data bit width 2bit (one clock cycle transmits 2bit data) 100Mbps=50 MHz *2bit 10Mbps is to use 10 cycles to sample data once, which is equivalent to 10Mbps=50MHz/10*2bit |
| SMII |
Serial MII 100Mbps/10Mbps interface; Further increase the Clock frequency to maintain the same rate as MII; |
RXD[1:0] TXD[1:0] TX_EN RX_ER CLK_REF CRS_DV |
Clock=125MHz Data bit width 1bit (1bit data is transmitted in one clock cycle) Serial data frame: 10bit per frame (8bit data+2bit control) Control bits need to be removed when calculating effective bandwidth 100Mbps=125 MHz *（8bit/10bit） 10Mbps is to use 10 cycles to sample data once, which is equivalent to 10Mbps=（125 MHz/10）*（8bit/10bit） |
| WWII |
On the basis of the MII interface, the data bit width and clock frequency are improved to become a 1000Mbps interface |
RXD[7:0]、TXD[7:0] TX_ER 、 TX_EN RX_ER 、 RX_DV GTX_CLK、RX_CLK CRS、COL |
Clock=125MHz Data bit width 8bit (8bit data is transmitted in one clock cycle) 1000Mbps=125 MHz *8bit |
| RGMII |
Simplified version of GMII |
RXD[3:0]、TXD[3:0] TX_EN RX_DV TX_CLK、RX_CLK CRS、COL |
Clock=125MHz The data bit width is 4 bits (in one clock cycle, the rising edge takes 0-3 bits of TX\RX, and the falling edge takes 4-7 bits of TX\RX, so 8bit data is actually transmitted in one clock cycle) 1000Mbps=125 MHz *8bit 100Mbps=25 MHz *8bit 10Mbps=2.5MHz *8bit |
| SGMII |
Serial GMII, based on which the clock frequency is increased to 1000Mbps |
RXD[0]、TXD[0] RX_CLK |
Clock=125MHz Data bit width 1bit (1bit data is transmitted in one clock cycle) Serial data frame: 10bit per frame (8bit data+2bit control) 1000Mbps=125.0MHz *8bit However, the control bits need to be removed when calculating the effective bandwidth. |
Pay attention to the change of rate, because when we use TRI_MODE three-speed Ethernet IP, IP actually controls the MAC layer rate through the clock frequency.
In addition, when FPGA implements network communication, there is a special interface that has to be mentioned, that is SerDes. 10 Gigabit Ethernet communication is realized based on SerDes. We skip it here for now.
In the next article, we start to introduce the configuration of the IP core and the introduction of the interfaces used .