First introduce several commonly used attribute definitions, the syntax is:
/* synthesis, <any_company_specific_attribute = value_or_optional_value */
Note that the following two ways of writing are equivalent (verilog 2001 syntax),
(*preserve*) reg reg1;
reg reg1 /* synthesis preserve */;
When using wire, I personally generally use (*keep*) wire w1; this way of writing; sometimes I find that quartus cannot completely guarantee that some reg signals will not be synthesized, and I am very puzzled about the specific reasons. Record it for now.
The following are several commonly used Synthesis attributes of Altera,
Noprune
A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.
For example:
reg reg1 /* synthesis noprune */;
keep (this is mainly effective for wire)
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.
For example:
wire keep_wire /* synthesis keep */;
preserve (this is mainly for register)
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.
For example:
reg reg1 /* synthesis preserve */;
ram_init_file
A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory.
For example:
reg [7:0] mem[0:255] /* synthesis ram_init_file = " my_init_file.mif" */;
ramstyle
A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.
M512", "M4K", "M9K", "M144K", "MLAB", "M-RAM”
For example:
reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M512" */;
translate_off or translate_on
Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
For example:
parameter tpd = 2; // Generic delays
// synthesis translate_off
#tpd;
// synthesis translate_on
The state machine has the following three comprehensive attributes:
full_case A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".
Only used in Verilog, used with the case statement to indicate that all possible states have been given values that do not require other logic to hold signals.
module full_case (a, sel, y); input [3:0] a; input [1:0] sel; output y; reg y; always @(a or sel) case (sel) // synthesis full_case 2'b00: y="a"[0]; 2'b01: y="a"[1]; 2'b10: y="a"[2]; endcase endmodule
parallel_case A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.
Only used in Verilog, used with the case statement to force the generation of a parallel multiplex structure instead of a priority decoding structure.
module parallel_case (sel, a, b, c); input [2:0] sel; output a, b, c; reg a, b, c; always @(sel) begin {a, b, c} = 3'b0; casez (sel) // synthesis parallel_case 3'b1??: a = 1'b1; 3'b?1?: b = 1'b1; 3'b??1: c = 1'b1; endcase end endmodule
syn_encoding A Verilog HDL synthesis attribute that determines how the Quartus II software should encode the states of an inferred state machine. Forces to re-encode the state of the state machine. There are default, one-hot, sequential, gray, johnson, compact, user Encoding
(* syn_encoding = "user" *) reg [1:0] state; parameter init = 0, last = 3, next = 1, later = 2;
always @ (state) begin case (state) init: out = 2'b01; next: out = 2'b10; later: out = 2'b11; last: out = 2'b00; endcase end
In the above example, the states will be encoded as follows:
init = "00" last = "11" next = "01"
reference: