When FPGA FIR filter, is the most commonly used direct-type structure, easy, when direct type structure, the structure can select the serial / parallel structure (Lecture) / distributed architecture.
Multiply-accumulate operation of the serial FIR filter structure is serial, the data processing speed is slow. N serial order FIR filter, the input rate of the data processing system clock rate = / filter length (N + 1), the present Example 7 using serial order, the system clock 32 MHz, so that the input data rate (sampling rate is) to 4 MHz;
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7 stage serial FIR filter structure diagram shown in Figure, using only one multiplier, according to an input serial order of use of the multiplier,
the input signal is 1.8 MHz to 0.5 MHz superimposed signals, the sampling clock of 4 MHz (clock frequency of the system processing / filter order) 16-bit quantization;
filter coefficient quantizing 8-bit, 4 MHz sampling, low-pass filter (low pass filter, LPF), the cutoff frequency of 1 MHz, the design of the window function, Blackman window;
the input signal is a signal of 0.5 MHz, 16-bit truncation;
1. Create a new project and file
(1) New Verilog file, the input signal 16-bit, output signal of the 16-bit, low-level reset reset rst_n;
(2) the definition and assignment x0 ~ x8;
shift data at the rising edge of the data input clock data_clk operation, a low level reset initialization x0 ~ x8 are 0, rst_n shift operation data (see block diagram of the beginning of the note) is high;
(3) obtaining the filter coefficients h0 ~ h8;
Lecture accordance fdatool manner using the toolbox matlab design FIR lowpass filter, the coefficient is set to 8-bit quantization, the sampling clock 4 MHz (4MHz = 32MHz / 8 ), the cutoff frequency is set to 1 MHz (the lower cutoff frequency, the filter effect well, as used herein, the order of only 7 order, so the lower cutoff frequency re-established);
the 1.8 MHz signal is attenuated nearly -30 dB, the amplitude is a few percent of the original, solid and broken lines overlap almost completely, It indicates that 8-bit quantization of the filter coefficients does not substantially affect the filtering effect.
Deriving quantized parameters can be derived directly .coe backup file, matlab will automatically open the file after export factor, in Verilog-defined parameters h0 ~ h7 (note that there is a specified number of symbols);
(4) filtering the weighted summation
FIR output of the filter is convolution of input data and the filter coefficients of the different stages of the delay signal (multiply-accumulate operations), also corresponding to each input data have different delay weights, and weighting;
use a counter to count system processing clock clk counts, total number of 8 (0 to 7), each number corresponding to a multiplication process;
defined multiplier a / b / product:
reg signed [15:0] mult_a;
reg signed [7:0] mult_b;
wire signed [23:0] mult_p;
每个计数值对应相应的乘法器输入，这样共计 8 个 clk 时钟完成 8 次乘法操作，但是只是用了 1 个乘法器（在不同时间用的），节省了资源，但是速度较慢；
对乘法输出累加，在累加了 8 个值后，输出累加值并把原来的累加值清零；
2.使用 matlab 产生仿真信号
参数：
抽样频率 Fs = 4 MHz，信号 f1 = 0.5 MHz，信号 f2 = 1.8 MHz，具体参见 第三讲 Matlab 与 Vivado 联合仿真 FIR 滤波器；
红线部分前面乘0.5，让高频噪声信号的幅度小一些，这样滤波效果比较明显，不然 7 阶 FIR 滤波器的效果比较差；
3.编写仿真文件testbench
（1）例化模块；
（2）写 initial 块，初始化时钟、复位等；
（3）写 always 块，给出时钟翻转等；
（4）读写 .txt 文件，将 matlab 写好的 .txt 的数据赋给输入，把输出数据写入 .txt 文件给 matlab 分析；
具体见 第三讲 Matlab 与 Vivado 联合仿真 FIR 滤波器；
4.仿真
（1）Testbench仿真
阶数太少，滤波效果一般；
（2）Matlab仿真
分别是 f1、f2、f1+f2、滤波后的数据；
由于串行滤波器的速度限制，当处理频率较高的数据时，要求的系统时钟就需要更高，所以要想办法进行优化；
（1）观察 FIR 滤波器的系数可以发现，系数是对称的，这也是 FIR 滤波器对称结构的特性，对于本例来说，h0与h7一样，h1与h6一样…，则对于 data_in * h0 + x7 * h7 可以简化为 (data_in + x7) * h0，先计算对称的加法，再计算乘法，这样对于一个 7 阶的 FIR滤波器（8个滤波器系数），只需要计算 4 次乘法，在系统时钟和阶数不变的情况下，数据的输入速率可以由原来的 4 MHz提高到 8 MHz；或者说在输入速率和系统时钟不变的情况下，可以把阶数从 7 阶（8个系数）做到 15 阶（16个系数），使得滤波效果更好；
(2) The use of certain symmetry can improve the speed, but is still higher face higher needs of the system clock in order, then you can use the " resource exchange rate of thinking", parallel processing , and add lines, such consume more resources, but increase the speed;
Lecture Matlab co-simulation with Vivado FIR filter
Next time (6) - using Verilog realize the parallel FIR filter in Vivado -1
