(A) CPU function and basic structure
(Ii) an instruction execution process
The basic function and structure (iii) data path
Function and operating principle (d) of the controller
1. hardwired controller
2. The micro-program controller
microprogram microinstruction command and micro;
microinstruction encoding;
form a micro address.
(E) an instruction pipeline
Basic concepts of the instruction pipeline
2. The instruction pipeline to achieve substantially
Basic concepts and dynamic superscalar pipeline
Basic Concepts (six) core processor
(2009)
18. a computer instruction pipeline consists of four functional segments, each functional instruction flow through the time period (ignoring the various functional segments
buffer time between) are respectively 90ns, 80ns, 70ns and 60ns, the computer CPU clock cycles is at least
A. 90ns B.80ns C.70ns D.60ns
Answer: A
test sites: setting instruction pipeline stages
in order to give full play to the role of the pipeline, CPU clock cycles should take the maximum value of each function of the period of time, such that each of the functional segments can be performed under the unified control of the CPU clock. In this way, the execution time of each function segment of pipeline to be equal, without causing "clogging" or "stop" phenomenon, making a long period of time becomes the entire pipeline "bottleneck."
19 with respect to the micro program controller, a hardwired controller is characteristic
A. Slow instruction execution, the instruction modify and extend the functionality readily
B. Instruction execution is slow, modify and extend the functionality of the instruction is difficult to
C. Speed instruction execution, the instruction modify and extend the functionality of easy
D. Instruction execution speed, difficult to modify and extend the functionality of the instructions
Answer: D
characteristic test hardwired controller.
Hardwired control:
because of the speed control depends on the delay circuit, so faster.
Once the design is complete, it is impossible to add new features by other changes.
Microprogram control:
compared with the hard-wired controller, having regularity, flexibility, maintainability series of advantages.
Since the micro program controller uses the stored program principle, it should be taken once each instruction from the control memory,
and therefore affect the speed.
（2010）
19. The following instruction pipeline does not cause blocking is ()
A. bypass data
B. Data related to
C. conditional branch
D. resource conflicts
Answer: A
test sites: the cause of the instruction pipeline. Bypass incoming data is to solve the blocking instruction pipeline.
（2012）
18. A micro-computer controller program control mode, the operation of microinstruction control field using direct encoding method field, a total of 33 micro-command, constitute mutually exclusive categories 5, and 6 each include micro 7,3,12,5 command, the operation control field at least
A. 5 B. 6 bit bit bit C.15 D. 33
Answer: C
test sites: mutually exclusive concepts, since the need to consider the case of a non-send command, so each plus 1, so there 8,4,13,6,7 micro commands, logarithmic taken after a minimum operation control to obtain the entire field of 3 + 2 + 4 + 3 + 3 = 15
(2013)
A CPU clocked at 1.03 GHz, using 4-stage instruction pipeline, the execution of each pipeline stage requires one clock cycle. Provided that the CPU 100 performs the instructions, which execute the process, there occurs no pipeline stalls, pipeline throughput at this time is
A. 0.25 × 109 instructions / second instruction B. 0.97 × 109 / sec
C. 1.0 × 109 instruction / instructions D. 1.03 × 109 sec / sec
Answer: C
Resolution: 100 uses a four-pipeline instruction execution, the execution by the CPC + 4 (100-1) = 103 clock cycles (k + (n-1) ).
CPU frequency is 1.03 GHz, i.e. 1.03 G per clock cycle
pipeline throughput is 100 * 1.03G / 103
(2014)
A micro-computer 18. The controller program, a total of 32 instructions, instruction fetch common microprogram comprises two microinstructions, each instruction corresponding microprogram microinstruction average of four components, the use method to determine (the address field method) determining the address of the microinstruction, the microinstruction bits in the address field of at least:
a. 5. 6 B C D. 8. 9
answer: C
Analysis: microinstruction Article number = 2 + 32 = 130, the number can be taken at the 8 need to get used to represent the binary number microinstruction.
(2016)
19, known non-forwarding mechanism of the five sections of the basic pipeline (Fetch, decode / read register, operations, memory access and write back to the register), the following instruction sequence present data hazards instruction pair is ()
I1: the Add Rl, R2, R3; (R2) + (R3) -> Rl
I2: the Add R5, R2, R4; (R2) + (R4) -> R5
I3: the Add R4, R5, R3; (R3) + ( R5) -> R4
I4: the Add R5, R2, R6; (R2) + (R6) -> R5
A, I1 and I2 B, I2 and I3 C, I2 and I4 D, I3 and I4
answer: B
analysis: line It includes three kinds of risk: structural hazards, risk data, control risk. The data here adventure, popular point that is the consequence of the previous instruction is generated by the input of the next instruction
pipeline hazard
structural hazards
due to the competition of hardware resources, adventure where the operation can not be performed simultaneously. Such as memory access will result in construction adventure. IF stage and the MEM stage should involve memory access. Because access to the bus using a shared memory resources, can not operate simultaneously.
Data adventure
when the instruction to be executed depends on the data has not been processed, will lead instruction can not start right away, causing data adventure. ?-Through (Forwarding): the original write-back operation results in the WB stage, through means EX stage in the calculation result of the determination, to pass data directly to the next instruction.
Control adventure
there is a program jump statement, when the execution path of the program is to jump to a different address to execute, then the pipeline has been doing these fetch and decode work for nothing, which is controlled adventure pipeline. In this case, the processor needs emptying lines, jump to a new address re-enter the pipeline.
(2016)
2. Static pipeline means ()
A. Only one function pipeline
B. You can not change the function pipeline
C. While only one function complete line of multi-function
D. Can perform a variety of functions at the same assembly line
Answer: C
A pipeline can complete a fixed function, this function is called a single pipeline pipeline. Multifunctional pipeline refers pipeline segments may be different connections in the same time or different times, to achieve different functions in different connections.
In the multi-function pipeline, according to the same time it is able to connect in a variety of ways to perform multiple functions simultaneously, which can be divided into static and dynamic pipeline pipeline.
The so-called static lines, refers to the same period of time, each functional segment multi-function pipeline only in accordance with a fixed connected to achieve a fixed function only if all the tasks of the work in this way are out of line after, after the pipeline is completely empty, multi-function pipeline to reconnect to implement additional functionality.
Dynamic refers to the same line period, the segments can be connected in different ways multifunctional pipeline while performing a variety of functions. Of course, to achieve multiple simultaneous connections is conditional, i.e., the pipeline must not conflict between the various functional components.
1, the following statement is not correct ()
A. Linear line is a single function pipeline
B. Dynamic Pipeline is a versatile line
C. Static lines are versatile line
D. Dynamic single-function pipeline is the only pipeline
Answer: D
4. In flow machines, global correlation means ()
A. First read-after-write relevant
B. Read before write-related
C. Instructions related to
D. Caused by the relevant branch instruction
Answer: D
5. The water treatment machine associated global not included ()
A. Guessing method
B. formed in advance condition code
C. Accelerate the short cycle program executed
D. settings related to specific passages
Answer: D
Related dedicated channel is provided a method for solving local correlation is generated.