table of Contents
12.2.2 Control and Status Register
12.3.2.1 Data flow and fetch cycle
12.3.2.2 Data flow and indirect cycle
12.3.2.3 Data flow and interrupt cycle
12.4 Instruction Pipeline Technology
12.4.4 Handling branch instructions
12.1 CPU composition
Tasks to be completed by the CPU:
- Instruction fetch : The CPU must read instructions from the memory (register, cache, main memory).
- Interpret the instruction : the instruction must be decoded to determine the required action.
- Fetching data : The execution of instructions may require certain arithmetic or logical operations on the data.
- Processing data : The execution of instructions may require certain arithmetic or logical operations on the data.
- Write data : The result of execution may require data to be written to the memory or I/O module.
12.2 Register composition
The registers in the CPU can be divided into two categories: user-visible registers and control and status registers.
12.2.1 User visible registers
User visible registers can be divided into: general, data, address, condition code.
- General-purpose register (general-purpose register): Can be assigned by programmers for various purposes. Any general-purpose register can hold operands for any opcode. In some cases, general-purpose registers can be used for addressing functions.
- Data register: It can only be used to hold data and cannot be used to calculate the operand address.
- Address register: It can be some general purpose itself, or dedicated to a specific addressing mode. For example: segment pointer, index register, stack pointer.
- Flag register
12.2.2 Control and Status Register
1. For instruction execution, there are four types of registers that are essential: Program Counter (PC), Instruction Register (IR), Memory Address Register (MAR), and Memory Buffer Register (MBR).
- Program counter (PC): Store the address of the instruction to be fetched. Usually, after each instruction fetch, the content of the PC is changed by the CPU, so it always points to the next instruction to be executed.
- Instruction register (IR): stores the most recently fetched instruction. Analyze opcodes and operand specifiers in IR.
- Memory address register (MAR): Store the address of the memory location.
- Memory Buffer Register (MBR): Stores the data word to be written into the memory or the word recently read from the memory.
▲① Use MAR and MBR for data exchange with memory. In a bus-organized system, MAR is directly connected to the address bus , MBR is directly connected to the data bus , and then the user-visible register exchanges data with the MBR.
② ALU can directly access MBR and user visible registers.
2. Many CPU designs include one or a group of registers often called program status word (PSW). Usually PSW includes the following fields or flags:
- Sign (sign): Holds the sign bit of the final arithmetic operation result.
- Zero (zero): Set when the result is 0.
- Carry: If the operation causes the highest bit to have an upward carry (addition) or borrow (subtraction), it will be set. Used for multi-word arithmetic operations.
- Equal: Set if the result of the logical comparison is equal.
- Overflow: used to indicate arithmetic overflow.
- Interrupt enable/disable is used to enable or disable interrupts.
- Supervisor: Indicate whether the CPU is executing in supervisor mode or user mode. Certain privileged instructions can only be executed in supervisory mode, and certain storage areas can only be accessed in supervisory mode.
12.3 Instruction cycle
The instruction cycle includes the following sub-cycles:
- Fetch: Read the next instruction from the memory into the CPU.
- Execute: Interpret the operation code and complete the specified operation.
- Interrupt (interrupt): If the interrupt is allowed and an interrupt occurs, save the current process state and service the interrupt
12.3.1 Indirect cycle
The reading of the indirect address can be regarded as an additional instruction sub-cycle, and the process is shown in the figure below. The main line of action consists of alternate instruction fetching and instruction execution actions. After fetching an instruction, check it to determine whether indirect addressing is required. If it is, the required operand is fetched using indirect addressing. After execution, an interrupt may be processed before the next instruction is fetched.
The instruction cycle state diagram is as follows. Once an instruction is fetched, its operand specifier must be recognized. Then read each operand in the memory, this process may require indirect addressing. Register operands do not need to be read from memory. Once the operation is executed, a similar process may be required to store the result in main memory.
12.3.2 Data Flow
12.3.2.1 Data flow and fetch cycle
At the beginning, the PC stores the address of the next instruction to be fetched. This address is transferred to MAR and put on the address bus. The controller issues a memory read request, the memory puts the result on the data bus, the CPU copies it to the MBR, and then transmits it to the IR. During this period, the PC is incremented by 1 to prepare for the next instruction fetch.
12.3.2.2 Data flow and indirect cycle
Once the instruction fetch cycle has elapsed, the controller checks the contents of IR to determine whether there is a specifier that uses an indirect addressing operand. If yes, enter the indirect cycle. The rightmost N bit of MBR is an address reference, which is sent to MAR. Then, the controller requests a memory read, obtains the required operand address, and sends it to the MBR.
12.3.2.3 Data flow and interrupt cycle
The current content in the PC must be saved so that the CPU can resume its previous actions after the interruption. Then, the content of the PC is transferred to the MBR and will be written to the memory. For this purpose, a special memory location is loaded into the MAR by the controller. It may be a stack pointer. Subsequently, the address of the interrupt subroutine is loaded into the PC. As a result, the next instruction cycle will begin with this corresponding instruction.
Instruction fetching, indirection, and interrupt cycles are all simple and predictable.
12.4 Instruction Pipeline Technology
12.4.1 Pipeline Strategy
Consider the following decomposition of instruction processing:
- Instruction fetch (FI): Read the next expected instruction to the buffer.
- Decoding instruction (DI): Determine the opcode and operand designator.
- Compute operand (CO): Calculate the effective address of each source operand, which may involve offset addressing, register indirect addressing, indirect addressing, or other forms of address calculation.
- Fetch operand (FO): fetch each operand from memory. The operand in the register does not need to be fetched.
- Execution instruction (EI): complete the specified operation. If there is a specified destination operand location, write the result to this location.
- Write operation number (WO): Store the result in the memory.
The following figure shows such a 6-stage pipeline, which can reduce the execution time of 9 instructions from 54 time units to 14 time units.
Figure 12-11 illustrates the effect of conditional transitions, using the same procedure as Figure 12-10. Assume that instruction 3 is a conditional branch instruction that may go to instruction 15.
12.4.2 Pipeline performance
The cycle time T of the instruction pipeline is the time required to advance a group of instructions in the pipeline for a period of time. The time period can be expressed as:
Now suppose that n instructions are in progress and no transfer occurs. Let Tk,n be the total time required for the k-stage pipeline to execute all n instructions, then
The speedup ratio of using the instruction pipeline relative to not using the pipeline is defined as:
12.4.3 Pipeline adventure
There are three types of pipeline adventures: resource adventures, data adventures, and control adventures.
12.4.3.1 Resource hazard
Occurs when two (or more) instructions that have entered the pipeline need to use the same resources. The result is that in some part of the pipeline, these instructions must be executed serially, rather than in parallel. Resource hazard is sometimes called structural hazard.
Examples are as follows:
12.4.3.2 Data hazard
Occurs when there is a conflict in access to an operand location. The data hazard can usually be described in the following form: two instructions in the program are executed sequentially, and both will access the same memory or register operand. If the execution of the two instructions is strictly serial, then no problem occurs. However, if these two instructions are executed in a pipeline, it is possible that the operands will be updated out of order, resulting in a different result from strictly serial execution.
Examples are as follows:
There are 3 types of data adventures:
- Read After Write (RAW) or true dependency: One instruction rewrites a register or memory location, and subsequent instructions read data from the rewritten register or memory location. If the read operation starts before the write operation is complete, then a risk will occur.
- Write After Read (WAR) or anti-dependency (anti-dependency): One instruction reads a register or memory location, and subsequent instructions will rewrite the contents of the register or memory location. If the write operation starts before the read operation is completed, then a risk will occur.
- Write After Write (WAW) or output dependency: Two instructions need to rewrite the same register or memory location. If the write operations of these two instructions occur in the opposite order to the expected order, then a risk will occur.
12.4.3.3 Control hazard
Also known as a branch hazard, it occurs when the pipeline makes a wrong prediction of the branch and therefore reads an instruction that must be cancelled in the later stage.
12.4.4 Handling branch instructions
Several methods have been used to handle conditional branch instructions:
- Multiple streams
- Prefetch branch target
- Loop buffer
- Branch prediction
- Delayed branch
1. Multiple instruction streams
Copy the beginning of the pipeline and allow the pipeline to fetch these two instructions at the same time, using two instruction streams. There are two problems with this approach:
① If multiple pipelines are used, there will be competition delays for register and memory access.
②Before the original branch judgment is resolved, another branch instruction may enter the pipeline (no matter which way). In this way, the instruction stream needs to be added.
2. Prefetch branch targets
When a conditional branch instruction is recognized, in addition to the instruction following the branch instruction, the instruction at the branch target is also fetched. This goal is saved until the branch instruction is executed. If the branch occurs, the target has already been prefetched.
3. Buffer register
The buffer register is a small but extremely high-speed memory maintained by the instruction fetch stage of the pipeline, and contains n instructions fetched in the most recent order. If a transfer is about to occur, the hardware first checks whether the transfer target is in this buffer. If it is, the next instruction is fetched from this buffer.
4. Branch prediction
- Predict never taken
- Predict always taken
- Predict by opcode
- Taken/not taken switch
- Transfer history table (branch history table)
The first three methods are static, they do not depend on the past execution history of conditional branch instructions. The latter two methods are dynamic, and they depend on the history of execution.
5. Delayed branch