radio
1 (Single choice (2 points)) The register used to specify the main memory address of the instruction to be executed is______. (Single choice)
√A. Program counter PC
B. Instruction register IR
C. Memory address register MAR
D. Data buffer register
A. Program counter (PC, Program counter), used to store the address of the instruction.
B. Instruction Register (IR, Instruction Register), used to save an instruction currently being executed, including the instruction's opcode, address code, and address information.
2 (Single choice (2 points)) Among the following statements about microprograms and microinstructions, ______ is correct. (Single choice)
√A. Microprogrammed controllers are more flexible than hardwired controllers
B. The same microinstruction can issue mutually exclusive microcommands
C. All control signals generated by the controller are called microinstructions
D. Microprograms Controllers are generally faster than hardwired controls
B. (Analysis comes from Video 6.12 Microinstruction Format 03:55) The same microinstruction can only issue compatible microinstructions. Mutually exclusive microcommands: A series of output control signals output to the internal bus, these signals cannot be unique at the same time. Mutually exclusive uops can be compressed when encoded into uops. Example : For 7 microcommands that output numbers 1~7, 1 and 2 cannot be output at the same time, only one can be output at a time, so there is no need to encode 8 bits for this, just use 3-bit binary (3-8 decoder) that is Can express 7 messages.
It needs to be pointed out that 3-bit binary cannot represent 8 pieces of information, and the 0 state cannot correspond to a control signal , because no matter what the state is, after using the decoder, a bus output signal (high level) will be generated. The 0 state is indistinguishable from other states.
C. A microinstruction is a group of concurrent control signals (microcommands), and the C option is obviously nonsense.
D. slow. As shown below.
3 (single choice (2 points)) A computer adopts the micro-instruction format of the micro-program controller and adopts the coding method to organize, and a certain mutually exclusive command group is composed of 4 micro-commands, then the number of digits in the corresponding field in the micro-instruction register needs to be at least ( ). (single choice)
A. 5
B. 4
C. 2
√D. 3
Explain option B of the previous question. Because the 0 state cannot be used, 2 bits can only represent 3 microcommands, and 3 bits are needed.
4 (Single choice (2 points)) In the multi-cycle CPU, in the following descriptions about the relationship between instructions and microinstructions, the correct one is ( ). (Single choice)
A. Realize the mapping between instructions and microprograms through the form address field of instructions
B. Realize the mapping between instructions and microprograms through the addressing mode of instructions
C. The function of one instruction is realized by executing one microcommand
√D. The function of an instruction is realized by executing a microprogram
A, B. Wrong, the mapping is realized by fetching microinstructions in the control memory (controller memory).
C. Wrong, one instruction corresponds to multiple microinstructions.
D. Yes, a machine instruction corresponds to a microprogram in the control memory.
5 (Single-choice (2 points)) A single-cycle CPU with MIPS32 instruction architecture, its data path structure is as shown in the figure below When the instructions sub rd, rs, rt
are executed A. 1, 0, 1 , 0, 1 √B. 0, 1, 0, 0, 1 C. 0, 1, 0, 1, 0 D. 1 , 1, 0, 0, 0
Analysis: The number of PCSrc determines whether the next instruction address input to the PC is PC+4, or the relative address of PC+4+jump. As for how the relative address of the jump is calculated and seen, my answer is a blind guess based on the MIPS design concept. The data part of sub rd, rs, rt is a register, it is definitely not a relative address, so PCSrc=0.
regDst determines whether the input to Rw is consistent with Rb. This is obviously inconsistent. Wow, there are three registers. So regDst=1.
aluSrc decides whether to use the sign extension of the immediate value or the value read from the register, which is obviously 0.
memtoReg decides whether to use the value read from the memory or the previously calculated value. Obviously it is the calculated value, so it is 0.
RegWrite decides whether to write to Rw, obviously it needs to be written here, so it is 1.
For details, see the previous part of video 6.14. In summary, choose B.
6 (single choice (2 points)) Compared with the microprogram controller, the characteristics of the hard-wired controller are ( ) (single choice)
A. The instruction execution speed is slow, and the modification and expansion of the instruction function are easy
B. The instruction execution speed is slow , It is difficult to modify and expand the
instruction function C. The instruction execution speed is fast, and the instruction function modification and extension are easy
√D. The instruction execution speed is fast, but the instruction function modification and extension are difficult
multiple choice
1 (Multiple choice (3 points)) Among the following descriptions about instruction execution process control signal synchronization, the correct one is ( ) (Multiple choice) √A. The
synchronous control method will increase the CPI of the instruction
B. The same microcommand will not Different CPU cycles of the same instruction are valid multiple times
√C. Multiple control signals are allowed to be valid at the same time in the same clock cycle
√D. The synchronization method of the control signal may not be unique
A. Yes, the synchronous control mode means that each operation is synchronously controlled by a unified timing signal. This means that each micro-operation must be completed within the specified time, and the subsequent micro-operations are automatically executed when the specified time is reached. If the set clock cycle is longer, there will be waste for instructions that consume less time.
B. Wrong, an instruction corresponds to a microprogram, a microprogram has multiple microcommands, and a microcommand is composed of a group of microcommands. It is definitely allowed to repeatedly call the same microcommand.
C. Yes, one microinstruction corresponds to one clock cycle, and one microinstruction consists of a group of microcommands (control signals).
D. Yes, synchronous control can adopt a variety of schemes, among which the method of combining central control and local control is adopted. Arranging most of the instructions of the machine to be completed in a unified and relatively short machine cycle is called central control, while additional processing of some micro-operations in a few instructions with complex operations is called local control. Refer to Baidu Encyclopedia - Synchronous Control Mode .
2 (Multiple choice (3 points)) Among the following descriptions about the data path, the correct one is ( ) (Multiple choice)
A. General-purpose registers are state elements, but not included in the data path
√B. The execution of the data path The function is selected and controlled by the control signal sent by the control unit
√C. The data path is formed by connecting several operating elements and state elements
√D. ALU belongs to the operating element and is used to perform various arithmetic and logic operations
A. Wrong, including.
Everything else is right.
3 (Multiple choice (3 points)) Among the following descriptions about the instruction flow in the instruction fetch phase, the correct one is ( ) (Multiple choice) √A. The instruction fetch
process includes instruction fetch and PC incremental process
B. The instruction fetch process There is only one data path
in √C. The bus structure in the CPU affects the instruction fetch process
√D. Different PC increment methods affect the instruction fetch process
Data path: The path through which data is transmitted between functional components is called a data path, and the components on the path are called data path components, such as ALU, general-purpose registers, etc.
B. Wrong, there are two options for taking an immediate value or taking a simple PC increment.
A, D. Yes, you can see the 5th question of the above multiple-choice question, it is true.
C. Yes, for example, by adding a DMA (direct memory access) bus, it is possible to fetch instructions from the Cache. You can refer to the blog CPU composition structure .
4 (Multiple choice (3 points)) Among the following statements about the comparison between multi-cycle data path and single-cycle data path, the correct one is () (Multiple choice) √A. During the execution of an instruction, the single-cycle data
path Each component can only be used once, and the same component can be used multiple times in multiple cycles
√B. During the execution of the instruction, the effective control signal value in the single-cycle processor remains unchanged, while the multi-cycle processor The value of the effective control signal in may change
√C. Some devices can be multiplexed in multi-cycle
D. The CPI of a single-cycle processor is always greater than the CPI of a multi-cycle processor
Single cycle is hardwired, multicycle microprogramming and hardwired are both fine.
B. Yes, a single cycle is hardwired, one clock cycle corresponds to only one state, and an instruction must be completed within one clock cycle, which is a pure combinational logic; multi-cycle time sequence, an instruction can be completed within multiple clock cycles , after the input signal changes, the executed micro-command will be switched, and the value of the control signal may change.
A, C. Yes, some devices can be reused during multiple cycles. Each component in the single-cycle datapath can only be used once.
I find it strange that each part can only be used once in a single cycle, and maybe the next time the part is used, a new clock signal is required.
D. The CPI of a single cycle is always 1, its clock cycle is very large, and the CPI will not be very large.
5 (Multiple choice (3 points)) The following is a description of the design of the lw/sw instruction data path of the MIPS architecture. Which one is correct? ( ) (Multiple choice) √A. The "write enable" signal of the
data memory is in the lw instruction It is "0" when the instruction is executed, and it is "1" when the instruction sw is executed
. √B. The "write enable" signal of the register file is "1" when the instruction lw is executed, and it is "0" when the instruction sw is executed. √C
. In the lw/sw instruction data path, there must be a sign extension component for offset extension
√D. In the lw/sw instruction data path, the ALU control signal must be "add" (that is, the ALU does addition)
For the specific structure, please refer to question 5 of the radio.
A, B. lw wants to read the memory into the register, and AB must be right.
C. Yes, the immediate value is needed for memory calculation, so the sign extension component of the immediate value must be used.
D. Yes, both instructions need to calculate the address of the memory, and addition can be used. For details, please see 10:20 of video 6.14.
6 (Multiple choice (3 points)) Among the following descriptions about the instruction fetch operation parts, the correct one is ( ) (multiple choice) A.
In the single-cycle CPU data path, instruction registers need to be used to store and retrieve instructions√B
. Fetch The instruction operation can be performed simultaneously with the calculation operation of the next instruction address
√C. The delay of the instruction fetch operation is mainly determined by the memory fetch time
√D. The PC does not need the "write enable" control signal in the single-cycle data path
A. PC only.
B. Yes, two logics are enough. See question 5 of the radio for details.
C. Yes, reading and writing memory is often very slow, which is a limiting factor.
D. Yes, it is always 1.
7 (multiple choices (3 points)) The following is a description of the design of the R-type instruction data path of the MIPS architecture. Which one is correct ( ) (multiple choice) √A.
In the R-type instruction data path, there must be a The ALU is used to perform operations on register read data
√B. In the R-type instruction data path, there must be a general-purpose register group
√C with read and write ports. In the R-type instruction data path, there must be One path enables the ALU output to be sent to a register
√D. When executing an R-type instruction, the "write enable" control signal of the general register file must be "1"
right. From 5:38 of video 6.14.