First, the basic structure and function of the CPU
1, function
When using a computer to solve a problem, we must first write a program for him, the program is a sequence of instructions, this sequence should clearly tell the computer what to do, find the data used to operate in any place, once the program is loaded into memory , it can fetch the instructions to automate tasks and executing instructions by a computer. Used exclusively in this work is referred to as a central processor computer components, usually referred to as CPU.
CPU is dotted frame structure
CPU accesses the memory through an address bus or a data bus input and output ports.
ALU: performing a two numbers from the cache register DR accumulator AC from a calculation result is temporarily stored in the accumulator
Condition Status Register: Bit 0 Overflow flag and other flags
Buffer register DR: In this information out of the CPU has an extended stay, whether data or instructions to be advanced into the CPU cache register DR.
Instruction register: current instruction is being executed, the instruction here included opcode and address code, the operation code into the instruction decoder will know what to do instruction, instruction decoder to translate the results and timing controller tells the operator generator, and then send them to the execution command execution means of the computer in chronological order.
Program Counter: the next instruction to be executed address
Address Register: store the memory address of the CPU being accessed, and address bus directly connected to the general
A substantial portion of the CPU cache consists of three major operator and a controller.
Second, the process execution instruction
Basic concepts instruction cycle
Problem: The computer-readable instructions and data are stored in the memory inside binary code, computer Cantabile distinguish between the binary code is an instruction or data?
The computer automatically work out an instruction from memory and stored procedures in this instruction is executed, followed by another instruction fetch, execute instructions, again and again, constitute a closed cycle, except when the stop command, otherwise the cycle will continue indefinitely,
Instruction cycle: CPU removed from memory and executes an instruction that the sum of the instruction time, an instruction of different instruction cycles.
CPU cycle: also known as the machine cycle, with the shortest time an instruction word read from memory is defined
Clock cycle: often referred to beat or pulse period T, a cycle comprising a plurality of CPU clock cycles
eg: code execution analysis
The CLA; clear instructions, all the accumulated bits are cleared in register AC
ADD 30: addition instruction, the contents of accumulator 30 to the base of the contents of memory space AC adding
STA 40: the write address and the memory space 40
NOP: No Operation
JMP 21: jump instruction, the target address is 21
021-024 storing command, which is described single-address instruction, a CPU needs to fetch cycles
First instruction: not need to access memory, instruction fetch occupies one CPU cycle. Before performing the first PC content becomes 20, the cycle begins, instruction fetch, instruction address is 20, the address to access memory 20, an address register stores the memory address of the current CPU to be accessed, the address register and the address bus is directly connected , so the first step is to hungry 0 address register to the PC and then sent to an address bus (this time value is completed, an automatic, the contents of the PC 21 becomes ready for the next instruction), pass memory address bus, the address is read out from the memory 20 to the local instruction into the CPU via the data bus, the cache register DR in the months now, because now only the instruction fetch stage, it can be judged that the read instruction, because the instruction is so to speak sent to the instruction register IR, the instruction to be executed is the current information stored in IR, the instruction opcode information to the instruction decoder, the decoding operation of the controller and the results tell the timing generator, this time the operation controller and a timing generator ALU and accumulator want to issue an enforcement order. ALU will become the contents of the accumulator 0.
Second instruction: instruction fetch cycles occupies a CPU, an execution period occupies two CPU cycles. The current PC value is 21, first address register 21 to the PC, to the address bus, the contents of PC + 1'd, read out from the memory address 21 of the local add instruction, via the data bus buffer registers now the months, taking instruction stage, the instruction sent to the instruction register, and the operand sent to the instruction decoder, the decoding results to the operation of the controller and the timing generator, an add instruction operand in the accumulator 30, the other in the address unit, because access to the address data 30, it is necessary to pass the instruction register 30 through the internal bus address register, and since the address register is connected between the address bus, the memory address of the guide unit 30 the value of the the amount of data in the address 30 through the data bus 6 months of advanced buffer register, because the implementation stage, transmits the data to the ALU, the accumulator is fed as a further number of the ALU, the sum, and then writes the data back into the accumulator device.
The third instruction: write the number to access the memory, the current contents of PC are 22, we have to address access unit 22, a read command. First address register 22 to the PC, and the PC value becomes 23 + 1'd, via the address bus to the address of the instruction fetch unit 22 of the content, via the data bus to the buffer register, as is the fetch stage, Therefore instruction sent to the instruction register, instruction register code is sent to the operation instruction decoder, the instruction decoder controller and the operation result to the timing generator 40. the address to be written is passed through an internal bus 40 to the address register, the address is selected via the bus unit 40, the value of the advanced buffer 6 registers of the accumulator, via the internal data bus is written to memory.
Fourth instruction: PC Memory 23 is representative of a null operation, the PC 23 to the address register, via an address bus unit address to find the memory 23, the operation instruction via the data bus to the buffer register, to send to the instruction decoder, and then do nothing. It occupies a total of one CPU cycle.
Fifth instruction: PC memory 24 is sent to the address register 24, the address bus through the guide to find the address of the memory unit 24, via the bus to the instruction buffer register, as is the fetch stage, the instruction will be sent. to the command register. Then decoding,
The essence of the jump instruction jump address re-write back PC.
Example: The following is shown in FIG dual bus data path structure of the machine, IR the instruction register, PC of the program counter (having a self-energizing function), M main memory (by R / W control signal), AR address register, DR a data buffer register, the ALU by the addition, subtraction control signal that what operation is completed, the control signal G is a gate, Further, the line marked with small circles represent the control signal, the control embodiment yi y represents the input register signal, a control signal is output R1O register R1, is not marked character line for line uncontrolled
1) ADD R2, R0 instruction completion (R0) + (R2) -> R0 functional operation instruction cycle process which draw question, assuming that the instruction address into the PC, and lists the corresponding micro-operation control signal sequence .
A: cycle instruction fetch and execute instructions comprising
FETCH: The instruction address in the PC, (PC required instruction address to the address register) PCo G ARi
AR to reach the equivalent of an address bus, via memory address bus pass
Plus read control signal, CPU reads the contents of memory to the cache go in register (DR)
Instruction is an instruction sent to the command register: DRo B G A bus register write instruction bus IRi
Decoding
To the contents of R0 x R0o B bus G Xi
R2 Y R2o B content to bus G Yi
Connected only to the ALU control signal +
The result is stored in R0 R0 through bus B through G to R0
2）SUB R2 R3
Example Three, a 16-bit computer word length, fixed-length 16-bit instruction word a result, part of the data path structure shown in Figure, all the control signals in FIG. 1 is a valid, invalid is represented by 0, the control signal MDRInE as e.g. 1 enables data from the DB into the MDR, MDRin 1 represents allow data from the bus into the MDR, MAR has been assumed that the output is enabled.
Adding the ADD instruction (R1), R0 is a function (R0) + ((R1)) -> (R1) put the contents of R0 and R1 in the data memory unit of the data referred to primary and place the result into the guide within the meaning of the contents of R1 main memory unit saved.
The following table gives the command values and each street shooting decode stage (clock period) control functions and signals valid, press described manner are listed in the table with table instruction execution stage for each beat signal and effective control function
| clock | Features | Effective control signal |
| C1 | MAR<-(PC) | PCout Marina |
| C2 | MDR<-M(MAR) PC<-(PC)+1 | MemR MDRinE PC+1 |
| C3 | And <- (MDR) | MDRout |
| C4 | Instruction decoding | no |
Solution: Analysis
1. datapath comprises (a memory bus instruction calculator cpu)
2, CPU instruction cycle clock cycles cycles
3, the machine instruction ADD (R1), R0 meanings: (R0) + ((R1)) (R1)
4, a flow chart design instruction cycle
5, a list of instruction execution stage control signal
Second, the role and system timing signal
Timing signal: CPU in a similar schedule things so that the computer can accurately, quickly, methodical work.
Once the machine is started, i.e. CPU starts fetching and executing the instruction, the controller operation using a different order and pulse interval timing pulses, organized. What rhythmic command of machine movements required to do when the pulse on to, what to do when the pulse arrives, to various parts of the computer work needed to provide the time stamp.
Third, the working principle and function controller
Micro program controller: the operation control signal to write microinstructions into the read only memory (control memory), when the machine is running
Remove microinstructions one by one, resulting in the whole machine lock Xu various operation control signal, so that corresponding parts throughout the predetermined operation performed.
1. Micro commands and micromanipulation
Digital computer: the control means execution unit (controller) (arithmetic memory Peripherals)
Micro commands: to control the various components of execution unit sent by the control line control commands
Micro-operation: After performing the micro-command accepting an operation member performed
The control member and the contact member performs a control line and via feedback information.
Control means - "execution control line guide member
Execution means - the "Feedback control line guide member
Performing the reaction member to the operation of the control means through the feedback line to the control means according to the state by the execution unit to place a new micro-commands, called state test
Compatibility micro-operation: a colleague or within the same CPU cycle may execute in parallel micromanipulation
Exclusive of micro-operations: not colleagues or not in the same CPU may execute in parallel around a micro-operation
2, and the microprogram microinstruction
Microinstruction: In a CPU cycle of the machine, a set of micro-commands that achieve a combination of operational functions
Microprogram: implement a function of a number of machine instruction sequences consisting of microinstructions
1 = one machine instruction microprogram
Program - "command = {microprogram microinstruction micro command} {->} micromanipulation
Microinstruction basic format:
