(A) Instruction Format
1. The basic format of instruction
2. The fixed-length instruction format opcode
3. extended opcode instruction format
(B) addressing mode instructions
1. The concept of the effective address
2 and data addressing instruction addressing
3. Addressing common
(C) the basic concepts of CISC and RISC
2009
A 16-bit word length machine 16. The main memory byte prepared using relative addressing branch instruction, consisting of two bytes, the first byte is the opcode field, a relative displacement amount of the second byte field. It is assumed that an instruction fetch, each byte fetch PC is automatically incremented. If the target address of a branch instruction where the main memory address 2000H, the relative displacement amount field content is 06H, the branch instruction is successfully transferred
A. 2006h B.2007H
C. 2008H D.2009H
Answer: C
test sites: PC relative addressing mode
relative addressing EA = (PC) + A;
branch instruction is executed to fetch the first step, after the value PC2000H instruction fetch. Branch instruction consists of two bytes, each byte fetch PC is automatically incremented, so the fetch PC value 2002H, so EA = (PC) + A = 2002H + 06H = 2008H, so the answer is C.
17. The following account of the RISC, the error is
A. common RISC micro program controller
B. Most RISC instruction in one clock cycle
general purpose register number of the internal RISC relative CISC C. plurality
number of RISC instructions D. , the type of instruction formats and addressing modes relatively few CISC
Answer: A
difference between RISC and CISC instruction set: the test sites
RISC Reduced Instruction Set Features:
RISC reduced instruction set not simply but by simplifying the instructions cause the computer is simple and reasonable structure, thereby increasing the operation speed.
1, only a selected number of frequently used instructions and simple, but not useful for complex instructions, a small number of instructions.
2, the fixed instruction length, instruction format less, less addressing.
3, only the fetch / store instruction to access the memory number, the remaining instruction in the register, i.e., the memory access restriction.
4, CPU common to a considerable number of registers; Most instructions are completed in one machine cycle.
5, hardwired logic-based, no or little microprogram control.
6, with particular emphasis compilation, in a simple and effective way to support high-level language, reducing execution time.
2010
18. The following registers, the counter assembly language programmer-visible is ()
A. memory address registers (the MAR)
B. program counter (the PC)
C. store data register (MDR)
D. instruction register (IR)
Answer: B
test sites: the so-called visible, that is, the programmer can be actively modified.
2011
16. Offset addressing effective address is generated by adding the contents of a register address of a form. Following addressing mode, not offset addressing mode is
A. Indirect addressing B. Based addressing
C. Relative addressing D. Indexed addressing
Answer: A
test sites: offset addressing concept
relative addressing, indexed addressing, based addressing collectively referred to as offset addressing.
17. A machine has a flag register, wherein there is a carry / borrow flag CF2, the ZF zero flag, sign flag SF and the overflow flag OF, conditional branch instructions BGT (unsigned integer greater than Comparative transfer) transition condition is
A. CF + OF = 1 B. / SF + = the ZF. 1
C. / (CF + ZF) = 1 D. / (CF + SF) = 1
Answer: C
test sites: the meaning of the instruction flag
is determined unsigned integer A> B established, conditions that result is not equal to 0, i.e., the zero flag ZF = 0, and the comparison is of two numbers If the subtraction a> B will not cause a borrow, i.e., the carry / borrow flag CF = 0. Therefore, the correct option is C.
The remaining options used in the sign flag SF and the overflow flag OF, apparently can be ruled out. In fact, where SF = 0, OF = 0, so D is also true, but does not meet the requirements.
18. Instruction given following characteristics, it is conducive to the instruction pipeline is
I. Regular and uniform length instruction format
II. Boundary alignment according to instructions and data stored
III. Only Load / Store instruction to access the memory operand to
A. Only I, II B. Only II, III
C. Only I, III D. I, II, III
Answer: D
test sites: three or more RISC characteristic can effectively reduce the complexity of the instruction fetch or the execution, thereby facilitating the pipeline operation
19. And assuming no instructions using Cache prefetching, and the machine is in the "break open" state, then in the following statements about instructions executed, the error is
A. Each instruction cycle CPU access memory are at least one
B. Each instruction cycle must be greater than or equal to a CPU clock cycle
C. Any contents of the register instruction cycle operation instruction will not be changed in
D. It is likely to be interrupted by an external interrupt the current program execution at the end of each instruction
Answer: C
test sites: the basic concept, the use of registers, instruction cycle concept interrupted, even if the operation is empty, as long as the process of instruction fetch PC should be +1, so the contents of any register will not change the argument error.
2013
Suppose the contents of index register R is 1000H, the form of the instruction address 2000 H; content address 1000H is 2000H is, the content of the address 2000H is 3000H, the content of the address 3000 H is 4000H, the indexed addressing mode access to the operand is ()
A. B. 2000H 1000H 3000H D. C. 4000H
Answer: D 
2014
17. The computer has a 16 general purpose registers, 32-bit fixed-length instruction word operation code field (including addressing mode bit) is 8 bits, operand and destination operand source respectively Store instruction register direct addressing and group Indexed addressing mode, when the base register may be used any of general-purpose registers, and the offset is represented by complement, the Store instruction offset ranges
a -32768 -32767 ~ B ~ + 32767 + 32768
C -65536 ~ + 65535 D -65535 ~ + 65536
Title instructions 32, an 8-bit operation code (already contains addressing mode bit).
Using source operand register direct addressing can be used to mark which of four registers.
Destination operand address using group addressing, since a general purpose register may be used any, it is necessary to mark 4, so that the total number of offset station 32--8--4--4 = 16, so the answer is A.
2016
16. a following instruction format,
Wherein M is an addressing mode, I is the index register number, D is the form of an address, if using the first access between the indexed addressing mode, the operation is the effective address ()
A + D the I B. (the I) D +
C. ((the I) + D) D. ((the I)) + D
Answer: C
Resolution: Indexed addressing mode address between +
[2010] 43 title Exams (11 points)
in a computer-byte length is 16, the main memory size of 128KB address space, addressing by word. Using the word length instruction format, the instruction name field is defined as follows:
Transfer instruction uses relative addressing relative offset is represented by complement, addressing modes defined as follows:
Note: (X) represents a memory address X or register X, please answer the following questions:? (1) This instruction may have a maximum number of instructions? The computer has the maximum number of general purpose registers? Memory address register (MAR) and a memory data register (MDR) each need at least how many?
A: The instruction may have up to 16 instructions (OP4 position 2 . 4 = 16), the computer has a maximum of eight general purpose registers (Ms and Md are 3 bits), memory address register (MAR) and a memory data register ( MDR) are subject to at least 16. Because the size of 128KB address space, addressing by word, so that a total of 64K of memory cells, an address is 16 bits, so that at least 16 MAR; as word length is 16 bits, so that at least 16 MDR.
? (2) target branch instruction address range is the number of
A: destination address range of the branch instruction is 0000H ~ FFFFH. (16-bit instruction word)
(3) if the operation code represents the addition operation 0010B (mnemonic add), registers R4 and R5 are numbered 100B and 101B, R4 content is 1234H, R5 content is 5678H, the contents of the address 1234H is 5678H, the contents in the address 5678H is 1234H, the assembler statement "add (R4), (R5 ) +" ( source operand before the comma, comma destination operand) corresponding to the machine code is What (expressed in hexadecimal) after the instruction is executed, the contents of which registers and memory cells will change after change is what???
a: statement "add (R4), (R5 ) +" corresponding machine code : 0010 (opcode) 001 (register indirect) 100 (source operand) 010 (indirect register, increment) 101 (destination operand) B, hexadecimal representation 2315H.
Function of this instruction is: 1234H to the data memory unit and memory unit are summed 5678H, 5678H write the result back unit, and the contents of the memory address used after R5, R5 also executes content plus 1 operation, the "add (R4), (R5 ) +" after the instruction is executed, R5 and 5678H of the memory cell will change. After the execution, the contents of the R5 changed from 5678H 5679H. 5678H contents of the memory cell becomes the addition instruction and calculated: 5678H + 1234H = 68ACH.