Principles of Computer Organization focused summary

Numerical representation

The original code, complement, anti-code, frameshift

• Original code: Positive Negative 0 1 + number of machines [11111111, 01111111]
• Anti-Code: positive is the original code, the original code negated negative (except the sign bit
• Complement: positive numbers for the original code, negative anti-code +1 (symbol unchanged, unchanged last one on the right, left negated
• Shift: the sign bit code negated

Floating-point conversion

1. Decimal floating-point turn
   1. Binary transfer
   2. Normalization: = X * 2 ^ n-
   3. Order code offset value true value + n- = [exponent] Shift
   4. Floating point code: sign bit; order code; mantissa
2. Hex decimal floating-point turn
   1. Separating the sign bit; order code; mantissa.
   2. True value exponent n- = [exponent] shift - Offset
   3. Normalization: = X * 2 ^ n-
   4. Denormalized, for decimal

Decimal encoding

• 8421 yards: NBCD code, D = . 8 B3 + . 4 B2 + 2 B1 + . 1 b0,1010 illegal ~ 1111

• Code 2421: D = 2 B3 + . 4 B2 + 2 B1 + . 1 B0, of from 9 Complement : 9 to obtain the inverse complement (represented by 2421

• More than three yards: 8421 yards +0011 , no right ( "1" does not mean a fixed decimal value), of from 9 complement

• Gray: no right

  Decimal	Gray code
  0	0000
  1	0001
  2	0011
  3	0010
  4	0110
  5	1110
  6	1010
  7	1011
  8	1001
  9	1000

Packed decimal string:

8421 represents, a byte stored at the last two symbols, 1100 positive, negative 1101

-2648 expressed as

0000	0010	0110	0100	1000	1101

Data validation

Code distance: minimum variation between any two codewords binary

Parity: detecting an error code from 2

• Parity: number 1 is even -> 0 the number, 1 for odd -> 1 , bitwise exclusive or (0 = same, different = 1)
• Odd parity: number 1 is even -> a number, 1 for odd -> 0 , negated bitwise exclusive or, (all 0s does not exist
• Cross-parity

Hamming code: number of check bits K, the information bit N
$$
2 ^ {K}. 1-\ N + K + GEQ. 1
$$

• Pi check code assigned to 2 ^ (i-1), to form a new sequence
• Dii bit number ii = Σ [2 ^ (P new bit number -1)], namely: the blooming every new bit number = 2 ^ (check his respective parity bit number -1) Sum

Cyclic redundancy CRC: left N-1 bit arithmetic for generating 2, the remainder polynomial is added to the end of the original analog data

Numerical calculation machine

Complement addition and subtraction: the sign bit participate in operations

$$
[the Y X-+] {= complement} [X-] {complement} + [Y] _ {} fill
$$

$$
[the XY] {= complement} [X-] {complement} + [- Y] _ {} fill
$$

Overflow detection:

1. A sign bit: Xs = Ys = 0, Ss = 1 n overflowed; Xs = Ys = 1, Ss = 0 Overflow negative
2. Carry: Carry recorded as Cs, C1C2 ... Cn. C1 = 1, Cs = 0 Overflow positive; C1 = 0, Cs = 1 negative overflow
3. Deformation complement (double symbol bits): Ss1Ss2 = 00,11 no overflow; 01 positive overflow; negative overflow 10

Band shift symbols:

1. Original code: the symbol bit constant, positive and negative numbers are the complement 0
2. Complement: the sign bit unchanged
   1. Positive: 0 to fill the
   2. Negative: 0 up left, right up 1 (left plug 1, the right plug 0)

Fixed-point multiplication

Multiplying an original code: three registers: A high partial product storage, B deposit multiplicand, C multiplier storage
$$
product: P = \ left | X-\ right | + \ left | the Y \ right |
$$

$$
symbol: of P_ {S} {S} = X_ \ Oplus Y_ {S}
$$

1. Absolute value
2. 1 = lowest bit multiplier, multiplicand +; = 0, 0 +
3. After accumulating the partial products and the multiplier right one
4. Repeat 2,3
5. Symbol XOR, right Ny times for results

Complement a multiplication: Booth multiplication

1. Complement representation (the multiplicand and the partial product sign bit we take, take a single sign bit multiplier factor Y)
2. Multiplier increase append bit 0
3. Each time seeking partial product right time, decided to operate two lowest multiplier

Judge position	operating
0 0	+0 part of the plot, right one
0 1	Partial product + [X] fill, a right
1 0	Partial product + [- X] fill, a right
1 1	+0 part of the plot, right one

Two's complement multiplication:

• Correction method: the original code calculating, based on the results corrected

• Booth method:
  1. Complement representation (the multiplicand and the partial product take three symbol bits)
     1. Multiplier Y is an even number of digits, taking the sign bit 2, n / 2 + 1 AGO, n / 2 shift times, the last time does not shift
     2. Multiplier Y is an odd number of digits, taking the sign bit 1, (n + 1) / 2 times the accumulated displacement, a displacement of the last
     3. Summary: The two are the last to leave
  2. With a

Judge position	operating
0 0 0	+0 part of the original product, the right two
0 0 1	Primary partial product + [X] fill, two right
0 1 0	Primary partial product + [X] fill, two right
0 1 1	Primary partial product +2 [X] fill, two right
1 0 0	Primary partial product +2 [-X] up, two right
1 0 1	Primary partial product + [- X] fill, two right
1 1 0	Primary partial product + [- X] fill, two right
1 1 1	+0 part of the original product, the right two

Fixed point division

Alternative Method subtraction original code: 2 sign bits, three registers, A deposit dividend, B stored divisor, C storage supplier

1. Seeking | X |, | Y |, [| Y |] becomes complement; A = | X |, B = | Y |, C = 0, CR = 0
   
2. A = AB (+ [| Y |] becomes S)
3. 1. A> = 0 n: Cn = 1, A and C with a left, A = A + B
   2. A <0 Negative: Cn = 0, together with the left and a C 1 bit A, A = A -B
4. CR++
5. 1. ! CR = n: Back 3
   2. CR == n：
      1. A>=0正：Cn=1
      2. A<0负：Cn=0，A=A+B（+|Y|）

Complement subtraction alternative methods: the symbol bit 2, supra, the following [] are Complement

1. Seeking [X] fill, [Y] up, [- Y] Complement; A = [X], B = [Y], C = 0, CR = 0
   
2. 1. AB same number : A = A -B = [X-] + [-Y] (the same number -B, + B isobutyl No.
   2. AB 异号 : A = A + B = [X] + [Y]
3. 1. AB same number : Cn = 1, with the left and a C 1 bit A, A = A -B (same number -B, + B isobutyl No.
   2. AB different number : Cn = 0, together with the left and a C 1 bit A, A = A + B
4. CR++
5. 1. ! CR = n: Back 3
   2. CR == n: the end position 1, Cn = 1

Syllabus

Short Answer

1. Addressing

   A: register addressing, immediate addressing, direct, indirect, relative addressing, based addressing, indexed addressing

   Register: Location: the specified register. Method: the address code part of a given general-purpose register number stored in the register specified with the operand.

   Now: Position: address code field. Method: as long as the instruction is fetched operand to be removed for immediate use.

   Direct: Location: a main memory. Method: instruction address code field gives the address A is effective address of the operand.

   Indirect: Location: a main memory. Method: start main memory operand effective address extracted by the address code field in the instruction.

   Index: Location: a main memory. Method: The contents of the index register with the address given in the instruction form A are added to form the operand effective address.

   Base Address: Location: a main memory. Method: displacement amount of the contents of the base register and the instruction given; D are added to form the operand effective address.

   Relative: Location: a main memory. Method: providing a reference address of the program counter PC, the address field of the instruction code as the displacement amount D, the two operands to obtain the effective address added

2. cache or virtual memory address mapping mode

   Direct mapping, fully associative mapping, set associative mapping

   1. Direct mapping:
      • Features: each block of main memory can only be placed into the Cache only a specified position, if this position existing content, the conflict generation block, the original block will be swapped out unconditionally.
      • Advantages: low cost, easy to implement, fast speed address conversion
      • Disadvantages: not flexible enough, the probability of conflict Cache block highest, lowest utilization of space
   2. Fully associative mapping:
      • Features: Let any main memory block can be loaded into any of a Cache block position.
      • Advantages: flexible manner, the lowest probability of conflict Cache block, maximum utilization of space
      • Disadvantages: address conversion slow, costly
   3. Set associative mapping:
      • Features: The Cache divided into several groups, the main memory block direct image into any position within a corresponding group on the Cache (groups taken directly mapped, fully associative mapping taken in the group)
      • The advantages and disadvantages between full associative mapping and direct mapping of advantages and disadvantages.
   4. virtual memory cache similarities and differences
      • With: all need to address, or marker to judge. Cache memory is full or when the master should use the replacement algorithm.
      • Iso: Cache small capacity, only information saved in the main memory copy of the plurality of blocks perform the most urgent. Virtual memory to the main memory or secondary memory address space unified addressing, form a large storage space. In this large space, users can program freely. The virtual memory using an auxiliary hardware to identify the correspondence between virtual addresses and real addresses, and determines whether or not the memory cell indicated by this virtual address is loaded into the main memory. Cache Cache is labeled with a block number to access main memory address field, and compares the extracted tag field of address mark and a main memory. If equal, indicating effective access Cache, called Cache hit, if not equal, indicating that access Cache invalid, saying Cache miss or fail. Determining if virtual memory is already in main memory, by the address conversion, the CPU can directly access the actual main memory unit; if not in main memory, or put a block comprising a word of the main memory transferred then access by the CPU.

3. Chinese character GB code, area code, machine code, code font differences and relations

   GB code is a four-digit hexadecimal number, area code is a four-digit decimal number eleven, each GB code or area code corresponds to a single Chinese character or symbol , but because hexadecimal numbers rarely used, the area code is used, or kanji character is represented within the computer machine code

   GB code character encoding standard information is exchanged, but because the most significant bit is 0 before and after byte, ASCII code conflict occurs, and therefore difficult to use directly in the computer. Machine code characters using modification GB Code

   Character font code for a display screen or printer output kanji

Compute

1. Fixed-point arithmetic

2. Floating-point arithmetic

3. Magnetic storage media performance parameters calculated

   • $$
     data transfer rate = \ frac {} {capacity every time one rotation} (B / S)
     $$

   • $$
     average access time T_ {a} \ approx \ frac { 0+ channel between the mobile time \ Times (the number of tracks per side -1)} {2}
     $$

   • $$
     unformatted capacity density = maximum bit \ times the circumference of the innermost track \ times the total number of tracks
     $$

   • $$
     formatted capacity = sectors per track \ times the sector capacity \ times the total number of tracks
     $$

4. For display parameter calculation

   • $$
     video bandwidth horizontal resolution = \ times the vertical resolution \ times the field frequency \ times1.344
     $$

     1. Character display:

        1. $$
           a character window = (x + x_ {kerning}) \ times (y + y_ { spacing})
           $$

        2. $$
           Number of cache size (bytes) = OK \ times the number of characters per line
           $$

     2. CRT monitors:

        1. $$
           buffer capacity = the amount of a character frame
           $$

        2. $$
           a character generator capacity (ROM) = the number of ASCII characters displayable type \ Times. 8 (B)
           $$

        3. Random cache memory is stored in the ASCII

        4. Buffer address and Screen position: the position of the screen from left to right, top to bottom, the corresponding cache address from low to high, a character code corresponding to each address position of reality. Screen coordinates (X, Y), the buffer address = (X * 80 + Y)

        5. Characters stored in the font dot matrix, dot matrix display is read out line by line according to the ASCII character code.

        6. counter

           1. Point: + word interval between laterally spaced
           2. Word: x-character display line retrace level equivalent to +
           3. Line: spacing between longitudinally spaced rows +
           4. Row: y + column character vertical retrace and this

        7. Q graphical display information required for each pixel are stored in the VRAM, the display only ASCII characters to be displayed is stored in the VRAM, the dot matrix character from the character generator ROM

5. Bus relevant parameter calculation

   $$
   bus bandwidth B = data bus width W \ times \ frac {F} {bus clock frequency number N of clock cycles to complete one data transfer used}
   $$

   $$
   example test method: B = \ frac {bus width (bits)} {8 (bits / byte)} \ = Times operating frequency of a clock cycle transmitted bytes (bytes) \ Frequency Times
   $$

   • Factors bandwidth are:
     1. Bus Width
     2. Transmission distance
     3. Bus the transmission and reception circuit operating frequency limit
     4. Data transfer format

design

1. Design of memory (chip select word bit extensions

   • Bit extension: 64k X 1 → 64k X 8
   • Extended Word: 16k X 8 → 64k X 8
2. Microprogram or micro-designed sequence of operations

3. Interrupt priority setting and response