[Bus] Principles of Computer Organization

Bus Overview

　　Bus is a set of a plurality of members capable of time-sharing common information transmission line. And two time-sharing is a feature of the bus. It means sharing the same time a member is allowed only sends information to the bus, if a plurality of components in the system, they can transmit information to the time division bus. Sharing means may be a plurality of hook members on the bus, to exchange information between the various components can be time-shared by the set of lines. At a time allows only one member to transmit information to the bus, but a plurality of members can receive the same information from the bus.

 

　　Devices connected to the bus, its presence or absence of the bus control device and can be divided into two kinds from the main device. Master: the bus master device refers to the device to obtain control of the bus. Refers to a device from the master device is accessed, it can only respond to the master device sent to the various bus command bus: device.

 

　　Bus characteristics refer mechanical properties (size, shape), (and the timing relationship between signals) features (functions of each transmission line), and time characteristics of the electrical characteristics (transmission direction and effective level range).

 

　　In one bus cycle memory address bus transmission scheme of the plurality of successive data words, called a burst (Burst) transmission.

 

Computer system bus, functionally divided into the following three categories:

1. Chip bus. Chip bus is an internal bus of the chip, which is the common connection line, between the register and the ALU between internal registers and register CPU chip.
2. The system bus. The system bus is a bus between the functional components (CPU, main memory, I / O interface) within a computer system interconnected. Different system bus transmission of information content, can be divided into three categories: data bus, an address bus and a control bus.
   1. A data bus used to transfer data between the various functional components, which is a bidirectional transmission bus, and the number of bits word length, stores the relevant word length.
   2. It is used to indicate an address bus or I / O address of the main memory unit the data source or destination where the data on the data bus port, which is one-way transmission line, the size of main memory space and the number of bits of the address bus.
   3. The control bus is transmitted control information sent includes a CPU and main memory control command (or peripheral) returns the feedback signal to the CPU.
      A data transmission path formed by connecting respective functional components by a data bus called the data path. Represents the data path is the path data stream, the data bus is carried by the media.
3. Communication bus. The communication bus is a bus for transferring information between the computer system or computer system and other systems (e.g., remote communications device, test equipment), also known as the external bus communication bus.

Further, according to the timing control mode bus may be divided into a synchronous bus and an asynchronous bus, also by the data transfer bus is divided into a parallel format and serial buses.

 

 

 

Bus structure is usually divided into single-bus structure, a double bus structure and three bus structure.

1. Single-bus architecture. The single bus architecture CPU, main memory, I / O devices (via I / O interface) are hung on a set of buses, running directly exchange information between I / O devices, I / O devices and main memory. Direct exchange of information between the CPU and main memory, CPU and peripherals, without going through an intermediate device intervention.

    

    

2. Dual bus architecture. Dual bus architecture has two buses: a bus is the main memory for the CPU, main memory and data transfer between the channels; the other is an I / O bus, for transferring data between external devices and a plurality of channels. Advantages: low-speed I / O devices are separated from a single bus, memory bus and to achieve the I / O bus separation. Disadvantages: the need to increase the channel and other hardware devices.

    

    

3. Three bus architecture. Three bus architecture is the use of three separate buses between the components of the computer system to access configuration information, which are mainly three buses bus memory, I / O bus and direct memory access (DMA) bus. Main memory bus for transmitting address, data and control information between the CPU and memory. I / O bus for communication between CPU and various peripherals. DMA bus for transferring data directly between memory and high-speed peripherals. Advantages: improves the performance of I / O devices, so that faster response command, to improve system throughput. Disadvantages: low system efficiency.

    

    

Performance Bus

1. Bus transfer cycle. Refers to the time required for a bus operation (including application stage, addressing phase, transmission phase and end phase), referred to as bus cycle. Bus transfer cycle is usually composed of several bus clock cycle.
2. Bus clock cycle. I.e., the clock cycle of the machine. The computer has a single clock, to control the various components of the entire computer, but also have control over this bus clock.
3. Bus operating frequency. The frequency of various operations on the bus, the bus cycle rate. Actually refers to the data transfer times within one second.
4. The bus clock frequency. I.e., the clock frequency of the machine, which is the reciprocal of the clock period.
5. Bus width. Also known as bus width, which is the number of data bits can be transmitted on the bus at the same time, generally refers to the number of the data bus, referred to as 32-bit bus 32.
6. 总线带宽。可理解为总线的数据传输率，即单位时间内总线上同时能够传输的数据位数，通常用每秒传送的字节数来衡量，单位可用 B/s 表示。总线带宽 = 总线工作频率 * （总线宽度 / 8）。
7. 总线复用。总线复用是指一种信号线在不同的时间传输不同的信息，因此可以使用较少的线传输更多的信息，从而节省空间和成本。
8. 信号线数。地址总线、数据总线和控制总线 3 种总线书的总和称为信号线数。

其中，总线最主要的性能指标为总线宽度、总线（工作）频率、总线带宽，总线带宽是指总线本身所能达到的最高传输速率，它是衡量总线性能的重要指标。总线带宽 = 总线宽度 * 总线频率。例如总线工作频率为 22 MHz，总线宽度为 16 位，则总线带宽= 22 * （16 / 8）= 44 MB/s。

 

在总线上，同一时刻只能有一个主设备控制总线的传输操作。

 

总线仲裁

　　为解决多个主设备同时竞争总线控制权的问题，应当采用总线仲裁部件，以某种方式选择一个主设备优先获得总线控制权。只有获得了总线控制权的设备，才能开始传送数据。

　　总线仲裁方式按其仲裁控制机构可分为集中总裁方式和分布仲裁方式两种。

 

集中仲裁方式

　　总线控制逻辑基本上集中于一个设备（如 CPU）中。将所有的总线请求集中起来，利用一个特定的裁决算法进行裁决，称为集中仲裁方式。集中仲裁方式有链式查询、计数器定时查询方式和独立请求方式。

1. 链式查询方式。总线上所有的部件共用一根总线请求线，当有部件请求使用总线时，需经此线发总线请求信号到总线控制器。由总线控制器检查总线是否忙，若总线不忙，则立即发总线响应信号，经总线响应线 BG 串行地从一个部件传送到下一个部件，依次查询。若响应信号到达的部件无总线请求，则该信号立即传送到下一个部件；若响应信号到达的部件有总线请求，则信号被截住，不再传下去。

    在链式查询中，部件离总线控制器越近，其优先级越高；部件离总线控制器越远，其优先级越低。优点：链式查询只需很少几根控制线就能按一定优先次序实现总线控制，结构简单，扩充容易。缺点：对硬件电路的故障敏感，且优先级不能改变。当优先级高的部件频繁请求使用总线时，会使优先级较低的部件长期不能使用总线。

2. 计数器定时查询方式。它采用一个计数器控制总线使用权，相对链式查询方式多了一组地址线，少了一根总线响应线 BG。它仍共用一根总线请求线，当总线控制器收到总线请求信号并判断总线空闲时，计数器开始计数，计数值通过设备地址线发向各个部件。当地址线上的计数值与请求使用总线设备的地址一致时，该设备获得总线控制权，同时终止计数器的计数及查询。

    优点：计数可从“0”开始，此时一旦设备的优先级次序被固定，设备的优先级就按 0，1，...，n 的顺序降序排列，而且固定不变；计数也可从上一次的终点开始，即采用一种循环方法，此时设备使用总线的优先级相等；计数器的初值还可以由程序设置，故优先级可以改变，且这种电路的故障没有链式查询方式敏感。缺点：增加了控制线数（若设备有 n 个，则大致需要 ⌈log₂n⌉ + 2 条控制线），控制也相对比链式查询要复杂。

3. 独立请求方式。每个设备均有一对总线请求线 BR_i 和总线允许线 BG_i。当总线上的部件需要使用总线时，经各自的总线请求线发送总线请求信号，在总线控制器中排队，当总线控制器按一定的优先次序决定批准某个部件的请求时，给该部件发送总线响应信号，该部件接到此信号就获得了总线使用权，开始传送数据。
   优点：响应速度快，总线允许信号 BG 直接从控制器发送到有关设备，而不必在设备间传递或查询，而且对优先次序的控制相当灵活。缺点：控制线数量多（设备有 n 个，需要 2n + 1 条控制线，其中加的那条控制线为 BS 线，作用是让设备向总线控制器部件反馈已使用完总线），总线控制逻辑更复杂。

 

三种集中仲裁方式的区别与联系

对比项目\仲裁方式	链式查询	计数器定时查询	独立请求
控制线数	3（总线请求：1；总线忙：1；总线允许：1）	⌈log2n⌉ + 2（总线请求：1；总线忙：1；总线允许：⌈log2n⌉）	2n + 1（总线请求：n；总线忙：n；总线允许：1）
优点	结构简单；扩充容易；优先级固定	优先级灵活	响应速度快；优先级灵活
缺点	对电路故障敏感	控制线多，控制复杂	控制线多，控制复杂

 

　　分布式仲裁方式不需要中央仲裁器，每个潜在的主模块都有自己的仲裁号和仲裁器。当它们有总线请求时，就会把它们各自唯一的仲裁号发送到共享的仲裁总线上，每个仲裁器将从仲裁总线上得到的仲裁号与自己的仲裁号进行比较，若仲裁总线上的仲裁号优先级高，则它的总线请求不予响应，并撤销它的仲裁号。最后，获胜者的仲裁号保留在仲裁总线上。

 

 

“总线忙”信号的建立者是获得总线控制权的设备。

计数器定时查询和独立请求方式都可以使各个主设备得到总线使用权的机会基本相等，链式查询方式则不能。

 

总线操作和定时

一个总线周期通常可分为以下 4 个阶段：

1. 申请分配阶段。由需要使用总线的主模块（或主设备）提出申请，经总线仲裁机构决定将下一传输周期的总线使用权授予某一申请者。也可将此阶段细分为传输请求和总线仲裁两个阶段。
2. 寻址阶段。取得使用权的主模块通过总线发出本次要访问的从模块（或从设备）的地址及有关命令，启动参与本次传输的从模块。
3. 传输阶段。主模块和从模块进行数据交换，可单向或双向进行数据传输。
4. 结束阶段。住模块的有关信息均从系统总线上撤除，让出总线使用权。

 

同步定时方式

　　所谓同步定时方式，是指系统采用一个统一的时钟信号来协调和发送接收双方的传送定时关系。时钟产生相等的时间间隔，每个间隔构成一个总线周期。在一个总线周期中，发送方和接收方可以进行一次数据传送。因为采用统一的时钟，每个部件或设备发送或接收信息都在固定的总线传输周期内，一个总线的传送周期结束，下一个总线的传送周期开始。

　　优点：传送速度快，具有较高的传输速率；总线控制逻辑简单。缺点：主从设备属于强制性同步；不能及时进行数据通信的有效性检验，可靠性较差。同步通信适用于总线长度较短及总线所接部件的存取时间比较接近的系统。

 

异步定时方式

　　在异步定时方式中，没有统一的时钟，也没有固定的时间间隔，完全依靠传送双方相互制约的“握手”信号来实现定时控制。通常，把交换信息的两个部件或设备分为主设备和从设备，主设备提出交换信息的“请求”信号，经接口传送到从设备；从设备接到主设备的请求后，通过接口向主设备发出“回答”信号。

　　优点：总线周期长度可变，能保证两个工作速度相差很大的部件或设备之间可靠地进行信息交换，自动适应时间的配合。缺点：比同步控制方式稍复杂一些，速度比同步定时方式慢。

根据“请求”和“回答”信号的撤销是否互锁，异步定时方式又分为以下 3 中类型。

1. 不互锁方式。主设备发出“请求”信号后，不必等到接到从设备的“回答”信号，而是经过一段时间便撤销“请求”信号。而从设备在接到“请求”信号后，发出“回答”信号，并经过一段时间后自动撤销“回答”信号。双方不存在互锁关系。

2. 半互锁方式。主设备发出“请求”信号 后，必须在接到从设备的“回答”信号后，才撤销“请求”信号，有互锁的关系。而从设备在接到“请求”信号后，发出“回答信号 ”，但不必等待获知主设备的“请求”信号已经撤销，而是隔一段时间后自动撤销“回答”信号，不存在互锁关系。
   

3.  全互锁方式。主设备发出“请求”信号 后，必须在接到从设备的“回答”信号后，才撤销“请求”信号；从设备发出“回答”信号后，必须在获知主设备“请求”信号已撤销后，再撤销其“回答”信号。双方存在互锁关系。

   

半同步通信总线可以既采用同步方式又采用异步方式通信。

 

总线标准

 

 

 

 

 

 

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