Computer composition and design (RISC-V) - single-cycle implementation of data path and logic control
1 Introduction
In order to improve my understanding of the processor chapter in the book Computer Composition and Design (riscv), I wrote this blog.
2. Learn the basics
You need to understand the instruction set of riscv, how the instructions operate registers and memory, and the instruction formats of different types of instructions. The four command formats required for this chapter are listed below:
These four types of instructions are arithmetic, load, store and conditional branch.
3. Simple data path with control unit
As shown in the figure below:
We can see that the input of the control unit is the seven-bit opcode field in instruction[31-0], which is [6-0]. There are seven outputs, including two 1-bit signals that control the multiplexer (ALUSrc and MemToReg), three signals that control the register file and data memory reading and writing (RegWrite, MemRead, and MemWrite), and a 1-bit signal that determines whether to branch. bit signal (Branch) and a 2-bit control signal (ALUOp) of an ALU. The branch control signal is sent to an AND gate along with the zero input signal of the ALU.
Take add x1, x2, x3 as an example to explain how the data path and control unit are executed .
The instruction format of the add operation instruction is given below:
From this, we can know its data path operation:
First, the PC instruction is fetched from the instruction memory, and the PC is incremented by 4 through the Add arithmetic logic unit (Branch is 0, and PC+4 is executed unconditionally ).
Secondly, the 32-bit instructions are divided into control units, register files and arithmetic logic control units. The register file reads out the two registers x2 and x3, while the control unit calculates the control signals.
Finally, ALUSrc controls the multiplexer to be set to 0, and Read data1 and Read data2 are given to the ALU. ALU control allows ALU to perform addition, and the result is given to the multiplexer by ALU result. At this time, MemtoReg sets it to 0, and the result is written to register x1.
4. Summary
Although the single-cycle design structure is not complex and can complete instruction operations, its efficiency is too low. In this structure, the longest path determines its clock period, which would make it always too long, violating the design principle of accelerating recurring events.
However, by learning the single-cycle implementation of data path and logic design, we can well understand how instructions operate, which will help us in future learning and lay the foundation for designing processors.