Experiment content
1. Learn how to use Verilog HDL to design sequential circuits
2. Master the skills and methods of flexible use of Verilog HDL for various descriptions and modeling
3. Learn the working principles of data transfer and read/write of the register file, and master the design of the register file method
Solution
1. Analyze a 32x32-bit register file, which contains 32 registers, each with 32 bits. The register file has 2 read ports and 1 write port, that is, it can read the values of 2 registers at the same time and write to 1 register
2. First, analyze that the two ports read in are 5-bit addresses, and read out The data is two 32-bits. The register file has only one write port, and the control signal Write_Reg is required. The write operation is edge-triggered. All input signals for the write operation must be valid when the clock edge comes
. 3. Register file To decode the address of the read operation and write operation, you only need to quote the register address as the subscript of the array; read only requires combinational logic, give the register address, and read out the data
. 4. Code display:
top-level module (data input is required in Operation on the board):
module RegisterFile(Addr,Write_Reg,Opt,Clk,Reset,A_B,LED);
input [1:0]Opt;
input [4:0]Addr;
input Write_Reg,Clk,Reset,A_B;
output reg [7:0]LED;
wire [31:0]R_Data_A,R_Data_B;
reg [4:0]R_Addr_A,R_Addr_B;
reg [31:0]W_Data;
initial
LED <= 0;
Fourth_experiment_first F1(R_Addr_A,R_Addr_B,Write_Reg,R_Data_A,R_Data_B,Reset,Clk,Addr,W_Data);
always@(Addr or Write_Reg or Opt or A_B or R_Data_A or R_Data_B)
begin
if(Write_Reg)
begin
case(Opt)
2'b00: begin W_Data=32'h000f_000f; end
2'b01: begin W_Data=32'h0f0f_0f00; end
2'b10: begin W_Data=32'hf0f0_f0f0; end
2'b11: begin W_Data=32'hffff_ffff; end
endcase
end
else
if(A_B)
begin
R_Addr_A=Addr;
case(Opt)
2'b00: LED=R_Data_A[7:0];
2'b01: LED=R_Data_A[15:8];
2'b10: LED=R_Data_A[23:16];
2'b11: LED=R_Data_A[31:24];
endcase
end
else
begin
R_Addr_B=Addr;
case(Opt)
2'b00: LED=R_Data_B[7:0];
2'b01: LED=R_Data_B[15:8];
2'b10: LED=R_Data_B[23:16];
2'b11: LED=R_Data_B[31:24];
endcase
end
end
endmodule
Fourth_experiment_first module implemented by register file
module Fourth_experiment_first(R_Addr_A,R_Addr_B,Write_Reg,R_Data_A,R_Data_B,Reset,Clk,W_Addr,W_Data);
input [4:0]R_Addr_A,R_Addr_B,W_Addr;
input Write_Reg,Reset,Clk;
input[31:0] W_Data;
output [31:0] R_Data_A,R_Data_B;
reg [31:0] REG_Files[0:31];
integer i=0;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
for(i=0;i<=31;i=i+1)
REG_Files[i]<=0;
end
else
begin
if(Write_Reg)
REG_Files[W_Addr]<=W_Data;
end
end
assign R_Data_A = REG_Files[R_Addr_A];
assign R_Data_B = REG_Files[R_Addr_B];
endmodule
Test module
module Fourth_experiment_test;
// Inputs
reg [4:0] Addr;
reg Write_Reg;
reg [1:0] Opt;
reg Clk;
reg Reset;
reg A_B;
// Outputs
wire [7:0] LED;
RegisterFile uut (
.Addr(Addr),
.Write_Reg(Write_Reg),
.Opt(Opt),
.Clk(Clk),
.Reset(Reset),
.A_B(A_B),
.LED(LED)
);
always #20 Clk = ~Clk;
initial begin
Addr = 5'b00001;
Write_Reg = 1;
Opt = 0;
Clk = 1;
Reset = 0;
A_B = 0;
#100;
Addr = 5'b00001;
Write_Reg = 0;
Opt = 0;
A_B = 0;
end
endmodule