Bao Yungang, deputy director and researcher of the Institute of Computing Technology of the Chinese Academy of Sciences, announced on social media that the Chinese-led RISC-V open source processor "Xiangshan" has a new ownership - Beijing Open Source Chip Research Institute (Open Core Institute) . He said that after four months of preparation and construction after the establishment of the Kaixin Institute , the first batch of new projects around "Xiangshan" will now be launched, and other open source chip projects will be launched in succession.
Beijing Open Source Chip Research Institute is a private non-enterprise established in December 2021. It is an innovation consortium led and established by a group of industry leading enterprises and domestic top scientific research units. The research institute aims to build an open source chip technology system and accelerate the development of open source chip ecology. The research institute is committed to developing key common technologies in the RISC-V field, building key supporting platforms, optimizing ecological governance, promoting large-scale commercial use in key industries, accelerating the improvement and maturity of the RISC-V ecosystem, and creating a world-leading RISC-V industry ecosystem. The research institute will focus on the "Xiangshan" open source high-performance RISC-V processor core and the "One Core for Life" talent training plan.
Xiangshan is an open source high-performance RISC-V processor based on Chisel hardware design language and supports RV64GC instruction set. During the development of the Xiangshan processor, the team used a large number of open source tools including Chisel, Verilator, etc., to realize the basic tools for processor development such as differential verification, simulation snapshot, RISC-V checkpoint, etc., and established a set of The agile development process of processor front-end based on open source tools including design, implementation, verification, etc.
Fragrant Hill's architectural code is named after the lake. The first version of the architecture code is "Yanqi Lake", the second version of the architecture code is "Nanhu", "Nanhu" uses SMIC's 14nm process, the target frequency is 2GHz, the SPECCPU score reaches 10 points/GHz, and supports dual-channel DDR memory. Plus PCIe, USB, HDMI, and more.
Regarding the goal of "Xiangshan", Bao Yungang mentioned two aspects in his speech to the international community last year. One is to establish an open source RISC-V core like Linux and become a world-class architecture innovation platform . It can not only be widely used in the industry, but also support the experimentation of innovative ideas in academia; the second is to explore the agile development process of high-performance processors in the development process , and establish a set of high-performance processor design, implementation, and verification based on open source tools process, improve the efficiency of processor development, and lower the threshold for processor development.
In January of this year, Bao Yungang announced that the Xiangshan chip had been taped out. After returning the film, the serial port was adjusted. On January 24, Linux was successfully run.
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