5.4 Measuring and Improving Cache Performance
Cache association
There are three main mapping methods of Cache line: directed mapping, full associative, and set associative.
Reducing miss rate can be achieved through flexible mapping.
Directed mapping：
Each memory block can only exist in one cache line in the cache.
Every time a new memory block is loaded, a certain cache line must be replaced, and the miss rate is relatively high.
Full associative：
Each memory block can store all the cache lines in the cache.
When determining whether a cache is hit, more hardware resources are required; it is generally applicable to caches with fewer cache line numbers.
Set-associative group connected
Generally it is n-way set associative (n-way group connected).
Each set consists of n cache lines, and each memory block can be placed in any cache line of a certain set.
Way means that a memory block can be placed in several cache lines.
From another perspective, the three mapping methods are all set -associative, but the way is different
Locating block in set associative cache
In the set associative cache, the index field in the address is used to index which set, and which cache line in the set is determined by comparing the tags. The process of comparing tags is carried out simultaneously - if it is 4 way, then four comparators are required.
The figure below shows a 4way cache with a total of 256 sets.
Replacing block strategy
Generally LRU (least recently used)
Reducing the Miss Penalty Using Multilevel Caches
In particular, a two-level cache structure allows the primary cache to focus on minimizing hit time to yield a shorter clock cycle or fewer pipeline stages, while allowing the secondary cache to focus on miss rate to reduce the penalty of long memory access times.
the primary cache of a multilevel cache is often smaller. Furthermore, the primary cache may use a smaller block size, to go with the smaller cache size and also to reduce the miss penalty.
In comparison, the secondary cache will be much larger than in a single-level cache, since the access time of the secondary cache is less critical.With a larger total size, the secondary cache may use a larger block size than appropriate with a single-level cache. It often uses higher associativity than the primary cache given the focus of reducing miss rates.
reference:
1. Computer Composition and Design Fifth Edition ARM Edition