Experimental content
Design and implement an ALU.
lab environment
ASUS VivoBook + Windows10 + Vivado2019.2, the language is Verilog HDL.
Experimental requirements
1. Support at least 8 operations
2. Output 5 glyphs
3. Support left and right shift operation
4. Can support at least two rounding operations
experiment procedure
1. Top-level design
enter
output
2. Operations
3. Shift operation
4. Rounding operation
5. Design code
`timescale 1ns / 1ps
///
// Company: Beijing Institute of Technology
// Engineer: Yabin Shi
// Create Date: 2022/12/24 17:39:50
///
module mine(
reset, in0, in1, op, cut, out, overflow, zero, carryout, parity, signal
);
input reset;
//用于初始化置零
input[31:0] in0,in1;
//操作数
input[10:0] op;
//操作运算符
input cut;
output[31:0] out;
//运算结果
output overflow,zero,carryout,parity,signal; //溢出判断位、零值判断位、进借
位判断位、奇偶校验位、符号位
reg[31:0] out;
//标明为寄存器类型变量
reg overflow,zero,carryout,parity,signal;//标明为寄存器类型变量
always@(*)
//使用 always 语句进行运算
begin
if(reset)
//判断 reset 值，为 1 进行初始化，为 0 进行 ALU 运算begin
out=0;
overflow=0;
zero=0;
carryout=0;
parity=0;
signal=0;
end
else
alutask( in0, in1, op, cut, out, overflow, zero, carryout, parity, signal);
//把具体运算功能模块封装成一个任务
end
task alutask;
//运算任务定义
input[31:0] in0,in1;
input[10:0] op;
input cut;
output[31:0] out;
output overflow,zero,carryout,parity,signal;
reg[31:0] out;
reg tmp,pmt,overflow,zero,carryout,parity,signal;
begin
overflow=0;
//每次进行运算前，标志位置 0
carryout=0;
zero=0;
parity=0;
signal=0;
case( op )
11'b00000100000://有符号数加法
begin
{tmp,out}=in0+in1;
end
11'b00000100001://有符号数减法
begin
{tmp,out}=in0-in1;
end
11'b00000100010: out=in0&in1;//按位与
11'b00000100011: out=in0|in1;//按位或
11'b00000100100: out=in0^in1;//异或
11'b00000100101: out=~(in0|in1);//或非
11'b00000100110: out=( $signed(in0)==$signed(in1) )? 1:0;//有符号数
相等运算
11'b00000100111: out=( $signed(in0)>$signed(in1) )? 1:0;//有符号数比
较运算11'b00000000000: out=in0<<in1;
11'b00000000010:
begin
out=in0>>in1;
case( cut )
1'b0://恒舍
out[0]=out[0];
1'b1://恒置 1
out[0]=1;
endcase
end
11'b00000000011: out=in0>>>in1;
endcase
zero=out==0;
//zero 通过直接判断 out 是否为 0
carryout=tmp;
overflow=in0[31]^in1[31]^out[31]^tmp;
signal=out[31];
parity=~^out;
end
endtask
endmodule6. Simulation file
`timescale 1ns / 1ps
///
// Company: Beijing Institute of Technology
// Engineer: Yabin Shi
// Create Date: 2022/12/24 17:39:50
///
module mine1;
reg reset;
reg [31:0] in0,in1;
reg [10:0] op;
reg cut;
wire [31:0] out;
wire overflow,zero,carryout,parity,signal;
mine unit(
//模块实例化
.reset(reset),
.in0(in0),
.in1(in1),
.op(op),.cut(cut),
.out(out),
.overflow(overflow),
.zero(zero),
.carryout(carryout),
.parity(parity),
.signal(signal)
);
initial
begin
#10 reset=1;
#10 reset=0;in0=32'd3;in1=32'd2;cut=1'b1;
for(op=11'b00000100000;op<11'b00000100111;op=op+1)
#20;
#20 op=11'b00000000000;
#20 op=11'b00000000010;
#20 op=11'b00000000011;
#10 reset=1;
#10 reset=0;in0=-32'd1;in1=32'd2;cut=1'b0;
for(op=11'b00000100000;op<11'b00000100111;op=op+1)
#20;
#20 op=11'b00000000000;
#20 op=11'b00000000010;
#20 op=11'b00000000011;
#100 $finish;
end
initial
$monitor ($time,,,"reset=%b in0=%b in1=%b op=%b cut=%b out=%b overflow=%b
zero=%b carryout=%b parity=%b signal=%b",
reset,in0,in1,op,cut,out,overflow,zero,carryout,parity,signal);
endmodule7. Circuit Diagram
8. Simulation waveform
9. Monitor monitor results
10. Experimental experience
In the process of this experiment, I practiced the computer composition principles and architecture content learned in the book, basically
This book has mastered the use of Vivado and the writing of design code and simulation code, and realized the precipitation and consolidation of knowledge.
The experience has benefited me a lot.
During the experiment, I encountered many difficulties and spent a lot of time learning software usage and programming specifications.
Finally I successfully completed the experiment. Among them, the "Verilog simulation code and
Constraint file writing" video is very helpful to me, this is also one of the few courses on the Internet that specifically introduces simulation code writing
Cheng, hereby recommend and thank you.
Project source code and experiment report: https://github.com/YourHealer/Principles-of-computer-composition-ALU.git