原文：RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem
Author: Agam Shah
Reprinted from: https://thenewstack.io/risc-v-finds-its-foothold-in-a-rapidly-evolving-processor-ecosystem/
The following is the text
But the open source processor architecture will need to find more support from the software dev community before it can rival x86 and ARM architectures in the data center: A wrap-up of RISC-V Summit in Barcelona.
But open-source processor architectures need more support from the software development community before they can compete with x86 and ARM architectures in the data center: Summary from the RISC-V Summit in Barcelona.
Developers have grown up hearing ARM or x86 being the guts of PCs and servers, but an alternative architecture called RISC-V is emerging.
Developers hear that ARM or x86 are the guts of PCs and servers, but an alternative architecture called RISC-V is emerging.
In the next few years, some companies will inevitably ship PCs and servers running on RISC-V processors. Those systems will likely run on Linux as Microsoft is not known to be developing a Windows OS for the architecture.
Over the next few years, some companies will inevitably ship PCs and servers running on RISC-V processors. These systems will likely run on Linux, as Microsoft is not known to be developing a Windows operating system for the architecture.
But there are big problems with the software ecosystem — the developer support is pitiful. RISC-V International, which is developing the chip architecture, talks more about hardware, with software a distant second in priorities.
But there's a huge problem with the software ecosystem - developer support is pathetic. RISC-V International, which is developing the chip architecture, talks more about hardware, with software being far ahead in priority.
Initial Support
Since its emergence close to a decade ago, RISC-V quickly gained the support of major chip makers, including Apple, which has put controllers in its Apple Silicon. About 10 billion chip cores based on RISC-V have shipped. Most recently, Meta announced an AI inferencing chip built on RISC-V architecture.
Since its emergence nearly a decade ago, RISC-V has quickly gained support from major chipmakers, including Apple, which has built the controller into its Apple silicon. About 1 billion RISC-V-based chip cores have been shipped. Recently, Meta announced the launch of an AI inference chip based on RISC-V architecture.
The chip architecture is often called a hardware equivalent of Linux. It is a free chip technology built on a contributor culture and the ethos of open source, in which a community works together to develop and improve the product.
The chip architecture is often referred to as the hardware equivalent of Linux. It is a free chip technology built on a contributor culture and open source ethos, where the community works together to develop and improve the product.
RISC-V is a free-to-license architecture, which means anyone can fork a version of the architecture into their own chip.
RISC-V is a freely licensed architecture, meaning anyone can fork a version of the architecture into their own chips.
Chips with RISC-V can be compiled like Lego blocks — companies that take the base architecture, and top it off with proprietary hardware blocks that may include accelerators for AI, graphics, or security.
Chips with RISC-V can be compiled like Lego bricks — companies that take the basic architecture and compile it with blocks of proprietary hardware that might include accelerators for AI, graphics or security.
“What was once an experiment, a prototype, is quickly moving into production,” said Calista Redmond, during a keynote at last month’s RISC-V Summit in Barcelona.
"What was once an experiment, a prototype, is rapidly moving into production," Calista Redmond said during a keynote address at the RISC-V Summit in Barcelona last month.
The structure of RISC-V makes it suitable for cloud native environments handling diverse applications and complex computing requirements.
The structure of RISC-V makes it suitable for cloud-native environments that handle a variety of applications and complex computing needs.
The minimal base instructions are designed to quickly offload applications such as AI and analytics to accelerators like GPUs or specialized math processors, which excel at such tasks.
The smallest base instructions are designed to quickly offload applications such as AI and analytics to accelerators such as GPUs or dedicated math processors, which are good at such tasks.
Chips from Intel and AMD are reaching their physical limits, and the flexibility of RISC-V provides a structure to move computing into the future.
Chips from Intel and AMD are reaching their physical limits, and the flexibility of RISC-V provides a fabric that will push computing into the future.
For example, RISC-V provides a pathway for new hardware architectures such as sparse computing, which is being researched by the Intelligence Advanced Research Projects Activity, in which processing units are closer to the data in storage or memory.
For example, RISC-V provides a path to new hardware architectures such as sparse computing, which is being investigated by the Intelligence Advanced Research Projects activity, where the processing unit is brought closer to the data in storage or memory.
The Barcelona Supercomputing Centre proposed the concept of merging CPU and memory in a RISC-V chip, which will reduce the memory bottleneck posed by machine-learning applications.
The Barcelona Supercomputing Center has come up with the concept of merging CPU and memory into RISC-V chips, which would reduce memory bottlenecks for machine learning applications.
“What we want from it — it is actually to do memory-intensive operations close to memory, like memcpy,” said Umair Riaz, a researcher at BSC, referring to the C++ function to copy memory blocks. Riaz also referenced the spinlock function, and mentioned the CPU executing those in memory will be more efficient and faster.
"What we want to get out of this -- it's actually doing memory-intensive operations near memory, like memcpy," said Umair Riaz, a researcher at the BSC, referring to the C++ function that copies blocks of memory. Riaz also mentioned spin lock functions and mentioned that CPUs that execute these functions in memory will be more efficient and faster.
“Executing functions locally you will eventually get performance and less [network] traffic because you are doing much more closer to memory,” Riaz said.
"Executing functions locally, you end up gaining performance and less [network] traffic because you're doing it closer to memory," Riaz said.
Writing applications for such complicated RISC-V chips may be a load for even the bravest programmers that want to code directly to the hardware. But Intel wants to provide the tooling needed for coders to start testing applications in simulated RISC-V environments.
Writing applications for such complex RISC-V chips can also be a burden for the most intrepid programmers who want to code directly to the hardware. But Intel wants to provide the tools coders need to start testing applications in a simulated RISC-V environment.
OneAPI
Intel’s Codeplay software unit recently announced the OneAPI Construction Kit, which includes tools for developers to test code in a simulated RISC-V environment on x86 PCs.
Intel's Codeplay software division recently released the OneAPI build kit, which includes tools for developers to test code in a simulated RISC-V environment on an x86 PC.
The Construction Kit’s signature feature is support for SYCL — which allows coders to write and compile applications regardless of the hardware architecture — and Intel is taking the first steps to bring RISC-V support to the parallel-programming framework.
A signature feature of the build kit is support for SYCL, which allows coders to write and compile applications regardless of hardware architecture, and Intel is taking the first steps to bring RISC-V support to parallel programming frameworks.
The kit includes support for Intel’s DPC++/C++ Compiler, which allows C++ code to be recompiled for use across multiple hardware architectures.
The suite includes support for the Intel DPC++/C++ compiler, which allows C++ code to be recompiled for use across multiple hardware architectures.
Developers can also test RISC-V code on Raspberry Pi-like developer boards or systems from companies such as Milk-V, and StarFive. Both companies offer high-performance 64-bit RISC-V systems with support for Linux.
Developers can also test RISC-V code on development boards like the Raspberry Pi or systems from companies like Milk-V and StarFive. Both companies offer high-performance 64-bit RISC-V systems that support Linux.
Support for Linux tools on RISC-V are tepid. Only a handful of packages are fully supported, and that includes Ubuntu OS, Gnu Toolchain, OpenvSwitch, Apache Nuttx, and Spidermonkey for Mozilla.
Support for Linux tools on RISC-V is tepid. Only a few packages fully support it, including Ubuntu OS, Gnu Toolchain, OpenvSwitch, Apache Nuttx, and Mozilla's Spidermonkey.
Many packages for RISC-V will work reasonably well, but are still not fully supported. For example, the RISC-V developer community in China reported that more than 80% of the packages in open source Fedora are now supported on RISC-V,
Many packages for RISC-V work well, but are still not fully supported. For example, China's RISC-V developer community reports that more than 80% of packages in open source Fedora are now supported on RISC-V.
Some key packages, such as Pytorch, GCC, TensorFlow, and OpenJDK will work, but are not yet fully supported. Support for open source applications like LibreOffice and Firefox are being built up. Google is accelerating its support of AOSP (Android Open Source Project) on RISC-V, which will be a big part of the next architecture specification.
Some key packages like Pytorch, GCC, TensorFlow and OpenJDK work but are not fully supported yet. Support for open source applications such as LibreOffice and Firefox is being built. Google is accelerating support for AOSP (Android Open Source Project) on RISC-V, which will be an important part of the next architecture specification.
RISC-V server chip makers Esperanto Technologies and Ventana Micro Systems have announced server chips for cloud computing, but have not talked much about software support or programming models. Esperanto has ported Meta’s Open Pre-Trained Transformer model to its RISC-V server.
RISC-V server chipmakers Esperanto Technologies and Ventana Micro Systems have announced server chips for cloud computing without much talk about software support or programming models. Esperanto has ported Meta's open pre-trained transformer model to its RISC-V server.
RISC-V International, which is developing the architectural spec, is trying to solve that problem with the establishment of the RISC-V Software Ecosystem, also called RISE, to create the underlying software tools and middleware for RISC-V systems. The initial backers include companies such as Google, Intel, Nvidia, Qualcomm, Samsung, and Ventana.
RISC-V International, which is developing the architectural specification, is trying to address this issue by establishing the RISC-V Software Ecosystem, also known as RISE, which creates the underlying software tools and middleware for RISC-V systems. Initial backers include Google, Intel, Nvidia, Qualcomm, Samsung and Ventana, among others.
Mark Himelstein, chief technology officer RISC-V International, at the summit talked about RISC-V taking a page from the cultural roots of Linux culture, with contributors contributing to the shared interests.
Mark Himelstein, Chief Technology Officer of RISC-V International, talked about RISC-V starting from the cultural roots of Linux culture at the summit, and contributors made contributions for the common good.
“That contributor culture means upstreaming on RISC-V and other communities where open source and open standards play a part,” Himelstein said, adding “that does not mean you are working on the pieces of the puzzle that are rapidly commoditizing.”
“This culture of contributors means being upstream in the community where RISC-V and other open source and open standards come into play,” Himelstein said, adding, “It doesn’t mean you’re working on a puzzle piece that’s being rapidly commoditized.
There is also no structure for hardware and software co-design that makes it easier for coders to use x86 and ARM systems. RISC-V first develops a hardware spec and Linux compatibility comes later. That is very different than Intel, which upstreams Linux drivers for a chip before it is released, which ensures the hardware is compatible with the latest build of the OS.
Hardware and software co-design is also unstructured, making it easier for coders to work with x86 and ARM systems. RISC-V developed the hardware specification first, and Linux compatibility came later. This is very different from Intel, which upstreams Linux drivers before a chip is released to ensure the hardware is compatible with the latest version of the operating system.
China, Tho
RISC-V’s software efforts also lack a force of nature like Linus Torvalds that can drive a project forward by sheer will. RISC-V also is not mainstream enough to attract an army of developers.
Software efforts in RISC-V also lack a Linus Torvalds-like force of nature that can drive projects forward through sheer will. RISC-V is also not mainstream enough to attract a large number of developers.
But it is a different scene with China, which is adopting RISC-V on a massive scale to create homegrown chips and reduce its reliance on Western technology. Developers in China are rolling up their sleeves and contributing coding to stand-up RISC-V compatible operating systems for Linux.
But unlike the situation in China, China is adopting RISC-V on a large scale to make local chips and reduce its dependence on Western technology. Developers in China are rolling up their sleeves and contributing coding to Linux's RISC-V-compatible operating system.
Their motivation is simple — an engineering focus is driving China’s RISC-V initiative, not politics, and there is plenty of motivation for developers to build OS support, especially with the latest Western chip technology out of sight due to export restrictions.
Their motivation is simple - engineering focus is driving China's RISC-V plans, not politics, and developers have enough incentive to build OS support, especially in a country that doesn't see the latest Western chip technology due to export restrictions situation.
Chinese companies are developing some of the most sophisticated RISC-V chips, and the community is adding support for more packages daily. Many of the core contributors to Fedora, Debian, Gentoo and Arch Linux, GNU toolchain, and Clang are in China.
Chinese companies are developing some of the most advanced RISC-V chips, and the community is adding support for more packages every day. Many core contributors to Fedora, Debian, Gentoo and Arch Linux, the GNU toolchain and Clang are based in China.
The RISC-V community in China is also leading a grassroots effort to bring support for ROCm — which is AMD’s parallel-programming framework — to RISC-V processors. AMD did not respond to requests for comment on whether it was involved in porting ROCm to RISC-V.
China’s RISC-V community is also leading a grassroots effort to bring support for ROCm (AMD’s parallel programming framework) to RISC-V processors. AMD did not respond to a request for comment on whether it is involved in porting ROCm to RISC-V.
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About HS-2
The HS-2 RISC-V universal motherboard is a standard mATX motherboard designed for developers jointly developed by Pengfeng Technology and its partners. It is pre-installed with a software package customized and developed by Pengfeng Technology for RISC-V high-performance servers. Including various standard benchmarks, GCC compilers supporting V extensions, computing libraries, middleware, and a variety of typical server applications.
The HS-2 RISC-V general-purpose motherboard is equipped with a domestic RISC-V 64-core processor (SG2042). SG2042 is the highest-performance RISC-V processor currently in mass production. It is mainly designed for the needs of high-performance computing and is suitable for large computing power application scenarios such as scientific computing, engineering computing, AI computing, and fusion computing.
