System architecture design professional skills·Computer composition and structure

现在的一切都是为将来的梦想编织翅膀，让梦想在现实中展翅高飞。
Now everything is for the future of dream weaving wings, let the dream fly in reality.

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1. Computer structure

1.1 CPU composition

• Operator
  ① Arithmetic logic unit ALU: arithmetic operations and logical operations on data
  ② Accumulation register AC: general-purpose register, providing a work area for ALU for temporary storage of data
  ③ Data buffer register DR: temporary storage of instructions or data when writing memory
  ④Status condition register PSW: stores status flags and control flags (controversy: some also classify it as a controller)

• Controller
  ① Program counter PC: stores the address of the next instruction to be executed
  ② Instruction register IR: stores the instruction to be executed
  ③ Instruction decoder ID: analyzes and interprets the opcode field in the instruction
  ④ Timing component: provides timing control signals

1.2 Von Neumann structure and Harvard structure

• Von Neumann structure
  The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory
  .
  Features:
  (1) Generally used in PC processors, such as I3, I5, and I7 processors
  (2) Instructions and data memory are merged together
  (3) Instructions and data are transmitted through the same data bus

• Harvard Architecture
  The Harvard architecture is a memory structure that separates program instruction storage and data storage. The Harvard architecture is a parallel
  architecture. Its main feature is to store programs and data in different storage spaces. That is, the program
  memory.
  Features:
  (1) Generally used in embedded system processors (DSP) digital signal processing (DSP, Digital Signal Processing)
  (2) Instructions and data are stored separately and can be read in parallel, with a high data throughput rate
  (3) There are 4 buses: data bus and address bus for instructions and data

1.3 Embedded chip

2. Storage system

2.1 Hierarchical storage structure

2.2 Cache

• The function of Cache: improve the rate of CPU data input and output, and break through the von Neumann bottleneck, that is, the data transmission bandwidth limit between the CPU and the storage system.

• In the computer storage system system, Cache is the layer with the fastest access speed.

• Cache is transparent to programmers.

• The basis for using Cache to improve system performance is the principle of program locality.
  temporal locality
  spatial locality

• Temporal locality : Once an instruction in the program is executed, the instruction may be executed again soon. The typical reason is that there are a large number of loop operations in the program.

• Spatial locality : Once a program accesses a certain storage unit, its nearby storage units will also be accessed soon. That is, the addresses visited by the program within a period of time may be concentrated in a certain range. A typical situation is that the program Executed sequentially.

• Working set theory : The working set is a collection of pages that are frequently accessed when a process is running.

example:

inti， j， s=0， n=10000；
for(i=1； i<=n； i++)
	for(j=1； j<=n； j++)
			s+=j；
printf("结果为：%d"， s) ；

If h represents the access hit rate to the Cache, t1 represents the Cache cycle time, and t2 represents the main memory cycle time. Taking the read operation as an example, the average cycle of the system using "Cache + main memory" is t3, then: t3
= hx t1+(1 - h) × t2
where (1 - h) is also called the failure rate (miss rate)

2.3 Main memory addressing

• Storage unit
  number of storage units = maximum address - minimum address + 1

• Addressed content
  is addressed by word: the storage unit of the memory bank is a word storage unit, that is, the minimum addressing unit is a word.
  Addressed by byte: the storage unit of the memory bank is a byte storage unit, that is, the minimum addressing unit is a byte.

• Total capacity = number of storage units * addressing content

• According to the required capacity of the memory and the capacity of the selected memory chip, the total number of chips required can be calculated, that is:
  total number of chips = total capacity / capacity of each chip

2.4 Disk management

Access time = seek time + waiting time
. Seek time refers to the time it takes for the magnetic head to move to the track;
waiting time is the time it takes for the sectors waiting to be read and written to move under the magnetic head.

The time to read disk data should include the following three parts:
(1) The time to find the track.
(2) The time to find a block (sector, that is, the rotation delay time.
(3) Transmission time.

• doubt? ? :
  Access time = seek time + waiting time (average positioning time + rotation delay) I think there is a problem with this formula.
  I think it should be: access time = seek time + rotation delay + time to store (or retrieve) disk sector content;
  if what is said above is correct, how should we understand it? If it is wrong, where is the mistake?

• Average Access Time refers to the average time it takes for the magnetic head to find the specified data.
  The average access time refers to the average time it takes for the disk head to find the specified data. Usually it is the sum of the hard disk's average seek time and average latency (waiting time). The average access time best represents the time it takes for the hard disk to find a certain data. The smaller the value, the better.

• Average access time = average seek time + average waiting time

2.5 Disk Scheduling

• First come, first served (FCFS)
• Shortest seek time first (SSTF)
• Scan algorithm (SCAN)
• Circular Scan (CSCAN) Algorithm

3. Data transmission control method

4. Bus

• A bus allows only one device to send at the same time, but allows multiple devices to receive. So the bus is in half duplex mode
• Half duplex and full duplex
• Serial bus and parallel bus

Bus classification:

• Data Bus (DataBus, DB): transfers data that needs to be processed or stored back and forth between the CPU and RAM.
• Address Bus (AB): used to specify the address of data stored in RAM (Random Access Memory).
• Control Bus (CB): transmits signals from the microprocessor control unit (Control Unit) to peripheral devices. great

5. CISC and RISC

6. Assembly line

• Relevant parameter calculation: pipeline execution time calculation, pipeline throughput rate, pipeline acceleration ratio, etc.
• Pipelining refers to a quasi-parallel processing implementation technology in which multiple instructions overlap during program execution.
  The simultaneous processing of various components is for different instructions. They can work on different parts of multiple instructions at the same time to improve the utilization of each component and the average execution speed of the instructions.
  
  
  
  
  Pipeline speedup calculation:
  

7. Check code

7.1 Parity check

• The encoding method of parity check code is: a check code is composed of several bits of valid information (such as a byte), plus a binary bit (check bit).

• Odd parity: The number of "1"s in the entire check code (valid information bits and check bits) is an odd number.
  Even parity: The number of "1"s in the entire check code (valid information bits and check bits) is an even number.

• Parity check can check for 1-bit errors and cannot be corrected.

7.2 Cyclic Check Code CRC

CRC check, error detectable but not error correctable.
Cyclic Redundancy Check (CRC, Cyclic Redundancy Check)

• The encoding method of CRC is: splicing r-bit check code after k-bit information code. The key to applying the CRC code is how to easily obtain the r-bit check bit (encoding) from the k-bit information bits, and how to determine whether there is an error from the k+r-bit information code.

• The coding rules of cyclic redundancy check code are as follows:
  ① Express the N-bit effective information to be encoded as polynomial M(X);
  ② Shift M(X) left by K bits to get M(X)×XK, which is free K bits in order to assemble the K bit remainder (i.e. check digit);
  ③Select a K+1 bit generating polynomial G(X), and divide M(X)×XK modulo 2;
  ④Shift left by K bits The valid information and the remainder R(X) are added and subtracted modulo 2, and concatenated into a CRC code. At this time, the CRC code has a total of N+K bits.

• Use the agreed generator polynomial G(X) to divide the received CRC code. If it is correct, the remainder will be 0; if a certain bit is wrong, the remainder will not be
  0. Different bit errors result in different remainders, and there is a unique correspondence between the remainder and the error bit sequence number.

What is modulo 2 division, and how is it different from ordinary division?
Modulo 2 division refers to division in which carry is not considered during the division operation.
For example, the modulo 2 division of 10111 by 110 is: