Design of small CPU based on proteus
Summary
This article introduces the design template of the small CPU and the functions estimated to be realized in detail, and then gives a detailed overview of the principle of the module. Afterwards, the project design was analyzed, and a complete presentation was made from the schematic diagram and circuit design diagram. After introducing the basic design framework, this paper conducts a detailed analysis of the design and implementation of each module in the project, including key modules such as ALU, CM, and MM, as well as the writing of test programs and arithmetic overflow (CF ) And so on a series of logo design . In the function analysis part, this article is mainly based on the well-written machine program, and gives the machine program burned in ROM and screenshots of key positions during runtime to show the correctness of the CPU implementation. At the same time, this article also shares the author's experience and lessons, including some problems and solutions in the experiment; it also shares some thoughts and reflections on the process obtained during the project design process. At the end of this article, the author made a summary of the project and left a message.
Keywords : proteus , CPU , machine instruction , microinstruction , memory , controller
Table of contents
Chapter II Project Preparation
2.4 Principles of some modules
3.1.1 Machine instruction design
3.1.2 Instruction addressing mode design
3.1.3 Operand Addressing Mode Design
3.3.1 Overall structure diagram
3.3.2 The circuit diagram built
Chapter Four: Project Realization
4.1. Implementation of Microinstruction Control Memory CM
4.2 Realization of arithmetic unit module
4.3 Implementation of the Memory Section (MM)
4.4 Compilation of test program and design of a series of flag words such as operator overflow (CF)
Chapter 5 Functional Test Analysis
5.4 Testing the NOT_NOTD program
6.1 Problems encountered in project design and solutions
6.2 Project design thinking and process summary
6.3 Project design summary and experience
Appendix 1: Common Instruction Format Table
Appendix 2: Microinstruction Sets Stored in Control Memory
text
Chapter 1 Preface
The principle of computer composition is the core professional basic course of computer majors, and it is also an important subject that we as computer majors should master well. Through computer composition principle theory courses and experimental courses, we not only learned about computer composition and a lot of theoretical knowledge related to computer architecture, but also learned to use Proteus to simulate and design software and hardware.
Comprehensive system design is a design experiment, which not only exercises the design ability of simple computer systems, but also tests innovative thinking, and further improves the ability to analyze and solve problems through design and implementation, which is of great significance to the learning and application of computer composition principles.
Therefore, at the end of the semester, according to the teacher's request, the design is based on the software proteus, and based on a series of knowledge learned in the computer composition principle theory class and experimental class, a small CPU is implemented as a course design to test the learning of the half-semester experimental class results. Although the small CPU sparrow is small and complete, it has basic CPU functions, including instruction control, operation control, time control, and data processing. It also realizes a series of instructions such as LOAD, JUMP, and ADD, and uses microprograms to control the program .
Chapter II Project Preparation
2.1 Goals
Based on the learned machine instruction set and microprogram flow chart as the basis, proteus design knowledge as a reference, a small CPU is realized. The specific design functions are as follows:
(1) The whole system can support automatic and single-step operation modes, can correctly execute the functions of the programs stored in the main memory, and display information on the main data flow and control flow through LEDs in a timely manner.
(2) Support arithmetic operations, logic operations, memory read and write, register indirect data transfer and other types of instructions;
(3) Support basic addressing modes.
(4) Support more than 10 instructions;
(5) A program of a given machine instruction set can be run, and the program execution function is correct.
2.2 Project function analysis
This is a relatively complex design task that needs to take into account many aspects, including both hardware and software levels. Each function is analyzed below
(1) The whole system can support automatic and single-step operation modes, can correctly execute the functions of the programs stored in the main memory, and display information on the main data flow and control flow through LEDs in a timely manner.
This function can be realized by designing a circuit including CPU, main memory, and system control module. The main memory is used to store machine instructions and data, the CPU is responsible for processing instructions and interacting with the main memory, and the system control module is used to control the operating status of the entire system (such as single-step operation or automatic operation).
For the LED display, you can connect specific data or control signals to the LED lights, and when these signals change, the LED lights will light up. For example, CPU register values (such as PC and IR) can be connected with LED lights to display information such as the currently executed instruction and instruction address.
(2) Support arithmetic operations, logic operations, memory read and write, register indirect data transfer and other types of instructions;
This function needs to implement multiple instructions, including arithmetic operation instructions (such as addition, subtraction, multiplication, division, etc.), logic operation instructions (such as AND, OR, NOT, etc.), memory read and write instructions, and register indirect data transfer instructions. These instructions can be implemented in a manner similar to the design of microinstructions, that is, each instruction is decomposed into multiple basic operations (such as register reading, addition, writing back results, etc.), and the control logic of the CPU executes these basic operations in turn.
(3) Support basic addressing modes.
This function needs to support multiple addressing modes, including immediate addressing, direct addressing, indirect addressing, relative addressing, etc. These addressing modes can be represented by specific codes in the instructions, and the control logic of the CPU decides which addressing mode to use according to the codes in the instructions.
(4) Support more than 10 instructions;
This function involves specific instruction design, and requires the design of no less than 10 instruction sets, covering multiple aspects such as arithmetic operations, logic operations, memory read and write, and data transmission. You can refer to common RISC instruction set design ideas to ensure that the instruction set is concise and clear, and can cover the core functional requirements.
(5) A program of a given machine instruction set can be run, and the program execution function is correct.
This function needs to implement the parsing and execution process of instructions to ensure that each instruction can be correctly parsed and perform corresponding operations according to the requirements of the instruction. To ensure the correctness of the program, it is necessary to design sufficient test cases to test the combination of different instructions and data to ensure that the program can be executed correctly.
In general, this comprehensive system design needs to consider multiple aspects comprehensively, including instruction design, hardware circuit design, control logic design, etc.
2.3 Project components
Since this experiment is a simulation experiment, the components are all simulation devices referenced in proteus
7SEG-BCD、7SEG-BCD-GRN
74LS273、74LS112、74LS138、74LS139、74LS157、74LS160、74LS161、74LS163、74LS175、74LS181、74LS192、74LS194、74LS240、74LS244、74LS273、74LS373、74LS374
74LS00、74LS04、74LS08、74LS10、74LS11、74LS32、74LS73、74LS74
2764、4078、6116
BUTTON、DIPSWC_8、LAMP、LED-GREEN、LED-RED、LED-YELLOW
OR、RES、RESPACK-8、SW-SPDT、74ALS244
2.4 Principles of some modules
(1) ALU module
ALU is an acronym for Arithmetic Logic Unit, which is an important part of the CPU. It is mainly responsible for implementing various arithmetic operations and logic operations, and transferring the results of operations to registers or other devices.
The ALU in the CPU usually consists of a set of processing devices, including adders, subtractors, comparators, shifters, etc. Through these processing devices, the ALU can implement various arithmetic and logic operations, such as addition, subtraction, multiplication, division, AND, OR, NOT, XOR, etc.
The ALU plays a vital role in the CPU. It is the core part of the CPU that can complete various data processing and calculations, and is responsible for processing a large amount of data and instructions. When the CPU needs to execute an instruction, it will send the instruction to the controller for decoding, then send the operand to the ALU for calculation according to the type of the instruction, and finally save the operation result to the register or memory.
In addition, the ALU is also responsible for implementing some control logic, such as conditional branches, jumps and other operations. These operations also need to be realized through the ALU, so as to realize the control of the program flow.
In short, the ALU is a very important part of the CPU. It can implement various arithmetic and logic operations, and is responsible for implementing program flow control. It is the basis for the CPU to complete various processing and operations.
(2) Microinstruction control memory CM
Microinstruction Control Memory (CM for short) is a kind of memory in the CPU, which is mainly used to store microinstructions. Microinstructions are some basic operations required when the CPU executes instructions, such as register reading, arithmetic operations, data transfer, and other operations. These micro-instructions are stored in the CM, and are executed by the CPU in a specific order to complete the execution process of the instructions.
Microinstructions control memory plays a very important role in CPU. It provides a programmable control method for the CPU, enabling the CPU to support various instructions and operations. By writing different microinstruction sequences, different operations and functions can be realized, so that the CPU has higher flexibility and scalability.
In addition, the microinstruction-controlled memory can also implement functions such as pipeline control and exception handling. By rationally designing microinstruction sequences, pipeline control can be realized and CPU execution efficiency can be improved; at the same time, by adding exception handling codes in microinstructions, various abnormal situations can be responded in time to ensure the correctness and stability of CPU.
(3) Memory section (MM)
The memory part of the CPU (Memory Management, MM for short) is a very important part of the computer system, and it is mainly responsible for managing the memory resources in the computer system. In a computer system, memory is a hardware device used to store data and programs, and the CPU needs to use MM to manage these memory resources and realize access and control of the memory.
MM plays several important roles in the CPU, including:
Memory allocation: When the CPU needs to load data or programs into memory, MM will be responsible for managing memory allocation. In the case of limited memory resources, MM needs to be able to manage memory efficiently, so as to use available memory resources as much as possible, thereby improving the performance and efficiency of the computer system.
Memory Protection: In a computer system, different processes may run concurrently, and these processes need to access data and programs in memory. In order to ensure the security and stability of each process, MM needs to be able to protect memory resources and prevent a process from accidentally destroying data or programs in other processes.
Virtual memory: In order to improve the performance and efficiency of the computer system, MM can also realize the function of virtual memory. Virtual memory is a technology that uses the space on the computer's hard disk as memory. It can save some infrequently used memory data or programs to the hard disk and load it when needed. Through virtual memory technology, MM can increase the memory usage of the computer system, thereby improving the performance and efficiency of the computer.
To sum up, the memory part (MM) in the CPU is a very important part of the computer system. It is mainly responsible for managing the memory resources in the computer system, including functions such as memory allocation, memory protection, virtual memory, and memory recycling. MM can improve the performance and efficiency of the computer system, thus playing a vital role in the operation of the entire computer system.
Chapter III Project Design
3.1 Project design content
3.1.1 Machine instruction design
The instruction design format this time follows the common instruction format design principles. The machine instruction occupies a total of 8 bits, of which the upper four bits are the operation code OP, and the lower four bits are the operand address ADDR. See the following description:
7——4 places OP
3——0 bit ADDR
3.1.2 Instruction addressing mode design
(1) Sequential addressing: According to the PC (74LS161) counter, the counter is automatically incremented by 1, and the next instruction is read sequentially;
(2) Jump addressing: According to the PC-SET function of the PC (74LS161), the data is preset into the counter according to the content of the jump instruction, so as to jump to the corresponding address.
3.1.3 Operand Addressing Mode Design
(1) Register addressing: use the AC (74LS373) register for addressing;
(2) Direct addressing: According to the address pointed to by ADDR in the instruction, the corresponding data in the main memory is obtained;
(3) Implicit addressing: Using the AC (74LS373) register, only one operand is provided for machine instructions that require double operands, and the other operand is implicit in AC.
See Appendix 1 for common machine instruction sets
3.1.4 Microinstruction Design
Microinstruction design idea: This design selects 12 instructions, which are common address operation, store storage instruction, load import instruction, jump jump instruction, addition, subtraction, and, or, not, address not, XOR and other operations order, and finally a shutdown order. Instructions are two-cycle and automatically executed.
Microinstruction design scheme: According to the specific circuit principle, it is decided to adopt 16 microprogram control points, and then realize the encoding of microinstructions by the value of each control point (that is, the value of each control point is 0 or 1), different instructions The codes of the corresponding control points will be different.
See Appendix II for the set of microinstructions stored in the control memory
It should be noted that the special point of this microinstruction set is that the microprogram design itself is simple, without setting the address field, and the microprogram corresponding to each machine instruction has only one microinstruction in the microprogram of the execution cycle to realize all operate. At the same time, the address of the microprogram in the control memory is directly identified by the OP code corresponding to the machine instruction.
I think there are pros and cons to such a design. The advantage is obviously that it is simple. Since there is no address field, naturally there is no need to realize the circuit logic responsible for the address transfer logic of the microinstructions and so on. But on the other hand, the disadvantages are also obvious. This kind of microprogram with only one microinstruction, the operations that can be realized are obviously very limited. However, in general, although this design is simple, it can also reflect the design and implementation principles of the microprogram CPU.
3.2 Instruction flow chart
Instruction flow in our actual implementation:
Of course, for the sake of simplicity in the above flow chart, the relevant control signals are not marked, and the clock control of the microcycle is not considered in the drawing.
3.3 Circuit Design
3.3.1 Overall structure diagram
The operation channel is a circuit composed of 181 for operation and 373 latches, including AC, DR1, DR2 and other designs. 6116 is used as the main storage and 2816 is used as the main control storage separation method for the storage access. At the same time, for the convenience of setting numbers, the data part of the instruction is directly connected with the input of 161.
3.3.2 The circuit diagram built
The division of each area in the above figure is as marked. Among them, CM is the micro-instruction control memory, MM is the main memory, CLOCK UNIT is the clock control signal unit, and CONTROL LOGIC is the concentrated area realized by the control logic circuit. TEST LAB is a test circuit that is not directly related to the main logic of this CPU. Most of it has been deleted, leaving only a small circuit for manually testing the working logic of the ALU chip.
The expression of the control logic is mainly as follows:
(The following uses & to indicate AND operation, || to indicate OR operation, and an overline to indicate non-operation, subject to the actual circuit)
Due to space limitations, other specific implementations will not be repeated here.
Chapter Four: Project Realization
4.1. Implementation of Microinstruction Control Memory CM
This part mainly discusses the discussion and realization of microinstruction control memory CM design. The micro-instruction control memory is used to store all the micro-programs that realize the entire instruction system, mainly using 74LS273 and 2764 chips.
Figure 4.1 Control memory
74LS273 is an 8D flip-flop with clear function, 1D~8D are data input terminals, 1Q~8Q are data output terminals, positive pulse trigger, low level clear
Figure 4.2 74LS273 pin diagram
2764 is a memory chip for storing data; A0 to A12 are 13 address signal input lines with a capacity of 8K, D0 to D7 are data lines, indicating that each memory unit of the chip stores a byte; CE is an input signal , low level is effective; OE is the output enable signal, low level is effective; PGM is the programming pulse input terminal, when programming the chip, the programming pulse signal is added from this terminal, and the value of PMG is 1 when reading data; Vpp is Power supply, which is +5V during normal operation.
Figure 4. 4 2764 truth table
4.2 Realization of arithmetic unit module
This part mainly discusses the discussion and implementation of the design of the arithmetic module (ALU module).
The data path of the arithmetic unit module (ALU module) is shown in the figure below:
In the path of the arithmetic unit, the data from the main memory MM is first entered into the uplink UP buffer 74LS244, and then into the latch DR1 (74LS373). The AC accumulator (74LS373) is a very important device in the arithmetic unit. It can be known from the instruction system that the AC is not only responsible for providing an operand of many operation instructions, but also storing the results of the operation. The 8-bit adder formed by cascading 2 pieces of 74LS181 is responsible for the operation, and the result is entered into DR2 (74LS373) to be latched, and finally entered into AC.
In this operation path, the reason why two components, UP and DOWN, are designed is to distinguish between reading data from the memory MM or storing data. However, due to some reasons, the store instruction in our group was not implemented in the end, so the DOWN component did not play its role, but it was still retained in order to make the arithmetic unit path more complete.
Through the above arithmetic unit path, functions such as addition, subtraction, AND, OR, and inversion of two 8-bit operands (one stored in the main memory storage unit specified by the instruction, and the other stored in AC) can be completed. In order to enhance the user experience, 2 digital tubes are specially set up to display the value of the AC accumulator. The final circuit diagram looks like this:
4.3 Implementation of memory section ( MM )
This part mainly discusses the discussion and function realization of the design of the memory part ( MM ) .
This part mainly includes two parts: PC, IR and main memory. PC—Program Counter is responsible for counting program warnings to ensure that the program can be executed continuously; IR—Instruction Register is responsible for temporarily storing the currently executing instructions. Main memory consists of ROM.
Since the format of the designed machine instruction is 7--4 bits OP 3--0 bits ADDR, only four bits of ROM are needed, why use ROM instead of others, the reason is: if we use Proteus, RAM cannot burn programs, Therefore, a RAM+ROM must be assembled as a memory. And in this case, since the machine instruction design is a 4-bit address code, if a RAM is added, the available space of the ROM is very little, and the number of test programs is limited. Therefore, our choice is to use a piece of ROM as the main memory, and still implement the control signals related to the store command, but in the absence of RAM, the write-back signal is invalid, that is to say, the execution of the store command will not affect the data in the memory. actual impact. At this point, the main memory design is completed.
For PC and IR, it is: the program counter PC is loaded with the address of the first instruction, and then the instruction is read from the finger memory to the IR according to the contents of the PC, and then the program counter is incremented by one for the next instruction prepare for. If a JMP instruction is encountered, the PC plus one operation is changed to enter the address specified in the IR into the PC, and then wait for the next instruction to be executed. The circuit diagram is as follows :
Next, analyze the read and write process and partial implementation of the memory
The conceived storage path is a separation method in which the 6116 is used as the main storage and the 2816 is used as the control storage. In this part of the path, a piece of 6116 is mainly used as the main memory, and its IO output data is buffered by a piece of 373, and then the high four bits are selected by a piece of 157 to be sent to the 395 chip as a register, and then sent to the 2816 chip as a control memory, the low four bits Pass back to memory as a data address, and read the operand.
4.4 Compilation of test program and design of a series of flag words such as operator overflow (CF)
Some of the test procedures for this experimental design are shown below.
Since the STORE instruction is not available
1.JUMP to 0111：
Before:
After taking out the JUMP instruction:
implement:
2. Execute LOAD 01H after the jump
5.3 Test overflow
cf_test program:
1.ADD 01H:
Before adding:
2. After adding 1:
5.4 Testing the NOT_NOTD program
program:
1. Initial LOAD 0AH:
NOT 0AH：
(result is F5H)
-
每一个测试程序都是单独的一个文件 //test1.asm这是测试（1-2+2）&3 ORG 0H DB 00010101 //LOAD 1(数存放在0101的地址中） DB 01000110 //ADD 2 DB 01010111 //SUB 2 DB 01101000 //AND 3 DB 11001111 //END DB 00000001 //操作数1 DB 00000010 //操作数2 DB 00000010 //操作数2 DB 00000011 //操作数3 //test2.asm这是测试跳转和load，store的程序 ORG 0H DB 00010011 //LOAD 0011 DB 00110111 //JUMP到0111 DB 10101010 //0011中原本存的数 DB 00000000 //0100中存的数 DB 00000000 //0101中存的数 ORG 7H DB 00010100 //LOAD 0100 DB 11001111 //END //test3.asm这是测试程序 [（8+7）加8] + 9异或6乘2与6减7 ORG 0H DB 00000000 //开始 DB 00011010 //LOAD 8 DB 01001011 //ADD 7 DB 01001010 //ADD 8 DB 01111100 //或 9 DB 10101101 //异或 6 DB 10111110 //乘 2 DB 01101101 //与 6 DB 01011011 //减 7 DB 11001110 //END DB 00001000 //操作数 8 DB 00000111 //操作数 7 DB 00001001 //操作数 9 DB 00000110 //操作数 6 DB 00000010 //操作数 2 下面是一个关于溢出测试的程序 cf_test.asm ORG 0000H DB 00010011B; LOAD FFH DB 01000100B; ADD 1 DB 11001111B; HLT DB 11111111B; NUM FFH DB 00000001B; NUM 1 ENDThe specific test file is as follows
-
The test program mainly tests the arithmetic operation and logical operation in the CPU, as well as the JUMP, LOAD and overflow flag bit tests. I first write the program according to the needs of our test program, then compile and generate a HEX file, and then burn the HEX file into the designed MM during the test, so that we can test against the program.
The content of this part of the design also includes standard words such as the overflow of the arithmetic unit (ALU). The main component of this part is a 74LS73. The 74LS73 is an 8D flip-flop with a clear function. When all bits are 0, it is judged by a NOR gate that ZF is 1, and when a CLK signal comes, enter ZF, and get SF and CF in the same way.
The relevant circuit design of flag words such as arithmetic unit overflow is shown in the figure below.
-
Chapter 5 Functional Test Analysis
The function test analysis part will be mainly based on the written machine program (stored in the PROGRAM folder of the project file), and will give the machine program programmed in the ROM and screenshots of key positions during operation to show the correctness of the CPU implementation.
5.1 Test test3 program
Mainly related to arithmetic instructions
program:
ORG 0000H DB 00011010B ;LOAD 0FH DB 01001011B ;ADD 08H 17H DB 01001010B ;ADD 0FH 26H DB 01111100B ;or 09H 2FH DB 10101101B ;xor 06H 29H DB 01101101B ;and 06H 00H DB 01011011B ;sub 08H F8H DB 11001110B ;END ORG 1010B DB 00001111B ;num 15 DB 00001000B ;num 8 DB 00001001B ;num 9 DB 00000110B ;num 6 EN1. Command: LOAD 0FH:
Before running LOAD
After running LOAD
2.ADD 08H：
ALU display after executing ADD 08H, the result is stored in DR2
The result is sent back to AC
3.ADD 0FH：
ALU display after executing ADD 0FH, the result is stored in DR1
As a result, call back to AC at 26 hours
- or 09H：
-
Execute command or 09H
The result is called back to AC
5. chorus 06H： -
test3-9 instruction xor 06
The result is called back to AC
6.and 06H：
-
Command and 06H
The result is called back to AC
7. Command sub 08H
under 08H：
The result is called back to AC
5.2 Test the test2 program
STORE_JUMP:
ORG 0000H DB 00011100B; LOAD 3 DB 00101101B; STORE (useless) DB 00110111B; JUMP to 0111 ORG 0111B DB 00011101B; LOAD 1 DB 11001111B; HALT ORG 1100B DB 00000011B; num 3 DB 00000001B; num 1 END -
ORG 0000H DB 00010011B; LOAD FFH DB 01000100B; ADD 1 DB 11001111B; HLT DB 11111111B; NUM FFH DB 00000001B; NUM 1 END -
ORG 0000H DB 00011010B ;LOAD 0AH DB 10010000B ;NOT 0AH F5H DB 10001011B ;NOTD 08H F7H DB 11001110B ;END ORG 1010B DB 00001010B ;num 0AH DB 00001000B ;num 08H END
NOTD 08H：
(result is F7H)
5.5 Test the Mulit_2 program
program:
MULTI 2
0AH before multiplying by 2:
Multiply by 2:
(result is 14H)
Chapter 6 Project Summary
6.1 Problems encountered in project design and solutions
(1) There were many problems in the process of doing this experiment, and the most impressive one was the execution of the jump instruction. Since I am more obsessed with the operation of instruction execution, it should be guaranteed to be done during execution, and I also think that this tricky approach may cause errors in other instructions, so many doubts arise. Then, after referring to the searched instruction set for analysis, I found that my approach should cause errors, and at the same time it is not very saving devices, and finally improved it.
(2) After the complete prototype of the memory and ALU is built, it is found that the 6116RAM we used cannot burn the program in Proteus, but if the ROM is used, the store command cannot be implemented, and the combination of ROM+RAM will increase Excessive complexity and can make the limited address space even tighter. Finally, after a long time of consideration, I decided to abandon the implementation of the store instruction and directly use ROM as the main memory.
(3) In the inspection of the ALU operation, it was clear that all the status bits were correct after repeated inspections during the operation, and the result of the manual test with another independent 181 chip was also correct. However, for the 181, there is no internal Timing chip, the same input can lead to different output. After modifying the order of several machines in the program, the operation of the same data is normal again, which is really incomprehensible, and it cannot be reproduced later. At present, I can only suspect that there are bugs in Proteus itself or problems in software cracking. Of course, it is not ruled out that I made a mistake in my operation.
6.2 Project design thinking and process summary
(1) The microprogram instruction set has been shown above. When I wrote it in the early stage, I thought it was enough to simply read the meter. Later, I found that the format was wrong, and it was completed correctly after several revisions. After the overall circuit is completed, the test of the test program is carried out. The programs for testing include test3.asm (testing LOAD, ADD, SUB, or, xor, and instructions), STORE_JUMP.asm (testing JUMP instruction), cf_test (testing overflow, symbol change, zero and three kinds of operation results), NOT_NOTD. asm (test NOT, NOTD instruction), Mulit2 (test multiplication by 2 instruction). Burn in each test program in turn, and take screenshots of the changes before and after the test (program screenshots in the result analysis), correct some minor errors in the program and the corresponding errors in the binary files generated by the burned-in program.
(2) At the beginning of this experiment, because I was not very familiar with the knowledge of the accounting group, there were many misunderstandings. However, the review stage at the end of the semester gave me a chance to correct these misunderstandings. I have a clearer understanding of the actual work to be done, and I also realize that it is necessary to practice the knowledge of the accounting group through such a large assignment in order to master it more firmly. When doing the actual circuit layout in Proteus, since I am not familiar with the use of Proteus, I spent a lot of time to get familiar with the fusion between the knowledge of the meter group and the actual operation of the software proteus.
6.3 Project design summary and experience
(1) First of all, in terms of learning knowledge, I feel that I have relearned metering.
In fact, I didn’t pay much attention to the counting group class for a long time before doing this big homework. Then, in order to complete the counting group 8086 experiment and this comprehensive design experiment, I spent a few days re-reading the relevant microprograms in the textbook. Chapters, I feel that the teaching materials are well written, and the explanation of the main points is very clear, which has greatly helped me understand the design of small CPUs. Through the practice of comprehensive system design, this knowledge has been further consolidated, and I have a clear understanding of the principle and design of the microprogram CPU. In addition, I also took this opportunity to learn the "high-level" operation of Proteus, and I am more proficient in the construction and simulation of circuit diagrams, and the writing and burning of test programs.
(2) Learned the relevant methods of program debugging, because this comprehensive design experiment is divided into various parts for design, so in the design process, many things are missing, such as the most typical, in the design process of the calculator In the above, our number and the part about the clock are missing, but we cannot guarantee that our design will be correct after we design it, so this requires certain debugging skills, such as using DIP switches to replace the clock signal And the source of the data, so that I can easily check the part of the design.
(3) I have learned and understood the knowledge about computer hardware design, and have a deeper understanding of computer composition and architecture. Even if I may not be able to engage in related work in the future, I still have a certain understanding of computers.
-
ORG 0000H DB 00011010B ;LOAD 0AH DB 10010000B ;NOT 0AH F5H DB 10001011B ;NOTD 08H F7H DB 11001110B ;END ORG 1010B DB 00001010B ;num 0AH DB 00001000B ;num 08H END -
epilogue
In this comprehensive system design of the computer composition principle course, I learned a lot, not only the knowledge in the textbook, but also the hands-on ability. Before doing the course design, I have done some related small experiments on proteus software, such as the design of arithmetic logic operator, adder, and 8086 minimum system, but they are all operated and verified according to the experimental steps and contents given by the teacher. Program, I did not build a CPU by myself because the model and design steps of the experimental circuit diagram were given before, and the use of proteus is limited to basic operations such as finding devices, basic mode connection, parent-child diagram comprehensive design, bus mode connection, etc. , I am not very clear about the function of some functions in the proteus software and the position of the chip, but in this course, because I have to find the chip by myself, I am more proficient in the use of proteus. There is also a deeper understanding of instructions, and a clearer understanding of the process of program operation. These are all knowledge beyond textbooks.
In short, in this course design, classroom knowledge has been consolidated, hands-on ability has also been enhanced, and a lot has been gained. Due to time constraints, I did not make more customized functions and extensions for this small CPU. If there is a chance in the future, I will definitely make it better.
At the end of the report, I would also like to thank Mr. Yuan for his guidance in the computer composition principle experiment class. Through these simulation experiments, I have a deeper understanding of theoretical knowledge and improved my practical ability. Although it is also the first time that you are responsible for the teaching of the computer composition principle experiment course, you still arrange for us calmly
Experimental tasks, let us learn knowledge, master ability, and get real improvement in the experimental class again and again!
references
[1] Lai Xiaozheng. Computer system experiment tutorial based on Proteus: logic, composition principle, architecture, microcomputer interface. Mechanical Industry Press, 2017.
[2] Qin Leihua, Wang Xiaolan. Computer composition principle experiment guidance and course design guidance (based on EDA platform). Wuhan: Huazhong University of Science and Technology Press, 2010.
[3] Qin Leihua, Wu Fei, Mo Zhengkun. Principles of Computer Composition. Beijing: Tsinghua University Press, 2011.
[4] DAVID A.PATTERSON (USA). Computer Composition and Design Hardware/Software Interface (The 3rd Edition of the Original Book). Beijing: Machinery Industry Press. 2007.
[5] Edited by Yuan Chunfeng. Computer Composition and System Structure. Beijing: Tsinghua University Press, 2011.
appendix
Appendix 1: Common Instruction Format Table
| Command full name |
instruction address |
command function |
| LOAD ADDR |
0001 |
Take the operand instruction, take out the operand in the memory unit pointed to by ADDR, and then put it into AC |
| STORE ADDR |
0010 |
Store back instruction, store the calculation result back into the memory unit MM pointed to by the address ADDR |
| JMP ADDR |
0011 |
Jump instruction, make the program jump to the unit pointed to by the address ADDR, and then read the next instruction (depending on PC) |
| ADD ADDR |
0100 |
Addition instruction, implement (AC) plus (ADDR), and put the result into AC |
| SUB ADDR |
0101 |
Subtraction instruction, realize (AC) minus (ADDR), and put the result into AC |
| AND ADDR |
0110 |
And instruction, realize (AC) & (ADDR), and put the result into AC |
| OR ADDR |
0111 |
Or instruction, realize (AC) & (ADDR), and put the result into AC |
| NOT ADDR |
1000 |
Invert the instruction, implement it, and put the result into AC |
| NOT |
1001 |
Invert the instruction, implement it, and put the result into AC |
| A XOR B |
1010 |
XOR instruction, realize (AC) XOR (ADDR), and put the result into AC |
| A added A |
1011 |
Multiply by 2 instruction, implement (AC) plus (AC), and put the result into AC |
| END |
1100 |
End instruction, the program terminates |
Appendix 2: Microinstruction Sets Stored in Control Memory
| instruction |
address |
Q15 STOP |
C14 LOAD |
C13 161_number |
C12 DR2_CONT |
C11 DR2_G |
Q10 AC_G |
C9 DR1_G |
C8 DOWN_244 |
C7 UP_244 |
C6 S3 |
C5 S2 |
C4 S1 |
C3 S0 |
C2 M |
C1 Cn |
C0 6116_WE |
| take address |
0000 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
| LOAD |
0001 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
| STORE |
0010 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
| JMP |
0011 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
| ADD |
0100 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
| SUB |
0101 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
| AND |
0110 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
| or |
0111 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
| NOTD |
1000 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
| NOT |
1001 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
| XOR |
1010 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
| multiply by 2 |
1011 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
| END |
1100 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
2023-06-18