1. Brief description
I won't introduce risc-v and hummingbird e203 in detail here, everyone should know better. The Hummingbird e203 project is relatively complete, and there is also a book introduction. The explanation is still very detailed. If you want to engage in digital IC or want to learn risc-v in the future, Hummingbird e203 is suitable for introductory learning.
However, the verification environment in the e203 project is iverilog, and vcs is commonly used in actual work. I personally think it is better to use the vcs environment to learn. If you have already worked, you are already used to the vcs environment, and you have to switch to iverilog when you study e203 in your spare time. Convenience. It's not that open source tools are not supported here. The main reason is that time and energy are limited after work, and you need to try to save learning costs.
Today, I will share how to modify the environment of Hummingbird e203 and use vcs+verdi to run. This EDA environment is what I shared before, Portal: Build your own digital IC EDA environment series of tutorials .
2. Git download
Open the terminal, use the following command to download, remember that the virtual machine is connected to the network.
git clone https://github.com/SI-RISCV/e200_opensource.git
The following is the directory of the e203 project. Let's enter vsim (verification directory) now. Leave the rest alone. The following sharing will be introduced slowly.
3. Modify the environment
Enter the bin directory of the
simulation , open the run.makefile simulation script and modify it as follows:
1) Modify the simulation tool, add the vcs simulation option, "LD_LIBRARY_PATH" is the path of novas, modify it according to your own environment.
2) Add verdi environment The
modified simulation environment is as follows:
RUN_DIR := ${PWD}
TESTCASE := ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi
DUMPWAVE := 1
VSRC_DIR := ${RUN_DIR}/../install/rtl
VTB_DIR := ${RUN_DIR}/../install/tb
TESTNAME := $(notdir $(patsubst %.dump,%,${
TESTCASE}.dump))
TEST_RUNDIR := ${TESTNAME}
RTL_V_FILES := $(wildcard ${
VSRC_DIR}/*/*.v)
TB_V_FILES := $(wildcard ${
VTB_DIR}/*.v)
# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors
SIM_TOOL := vcs#To-ADD: to add the simulatoin tool
#SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
SIM_OPTIONS := -timescale=1ns/1ns -fsdb -full64 -R +vc +v2k -sverilog -debug_all -P ${LD_LIBRARY_PATH}/novas.tab ${LD_LIBRARY_PATH}/pli.a -l vcs.log +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/ #To-ADD: to add the simulatoin tool options
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
# This is a free solution here to use iverilog to compile the code. Please NOTE!!!!
#
# Note:
# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded
# assertion in the RTL code because iverilog cannot support that syntax, if you
# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
#
# Here we didnt add macro "ENABLE_TB_FORCE"
# that macro was used to enable the random interrupt and bus-error insertion to make
# more intensive test in e200_opensource/tb/tb_top.v.
# Although the test become more intensive, the drawback is it makes the regression
# simulation running very slower, so by default now it is turned off.
# If you want to turn on them without caring the the regression speed,
# you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_EXEC := ../simv#To-ADD: to add the simulatoin executable
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
#SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
WAV_TOOL := verdi#To-ADD: to add the waveform tool
WAV_OPTIONS := -2001 -sv -top tb_top +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/#To-ADD: to add the waveform tool options
WAV_PFIX := #To-ADD: to add the waveform file postfix
all: run
compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
@-rm -rf compile.flg
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
touch compile.flg
compile: compile.flg
wave:
#gvim -p ${TESTCASE}.spike.log ${TESTCASE}.dump &
#${WAV_TOOL} ${WAV_OPTIONS} &
${WAV_TOOL} ${WAV_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} &
run: compile
rm -rf ${TEST_RUNDIR}
mkdir ${TEST_RUNDIR}
cd ${TEST_RUNDIR}; ${SIM_EXEC} +DUMPWAVE=${DUMPWAVE} +TESTCASE=${TESTCASE} |& tee ${TESTNAME}.log; cd ${RUN_DIR};
.PHONY: run clean all
4. Modify tb
Enter the tb directory, open tb_top.v and
add the following code. This is the wave file used by verdi.
initial begin
$value$plusargs("DUMPWAVE=%d",dumpwave);
if(dumpwave != 0)begin
// To add your waveform generation function
$fsdbDumpfile("ware.fsdb");
$fsdbDumpvars("+all");
end
end
5. Run the simulation
Enter the vsim directory, first execute the following command, the install directory will be generated, where the source code and tb are copied.
make install CORE=e203
Execute the following command to execute the simulation, and print "PASS" as shown in the figure below after the simulation is over.
make compile
make run_test
Run the following command to start verdi;
make wave
6. Summary
Modifying the simulation environment is relatively simple. Now you can use Verdi to learn RTL code, which will be much more efficient. This part is based on the EDA environment I shared before, and it will also be based on this environment in the future, so friends who want to learn together should use my environment. The official account backstage reply: EDA virtual machine can get a complete EDA environment (virtual machine) . I also uploaded this modified E203 project to gitee, portal: e203_mod , and the modified project later will also be uploaded to gitee.
