The project is implemented in a micro riscv processor core (tinyriscv), written in verilog language, just the easiest, most user-friendly way to achieve the function riscv instructions, and therefore did not intend to make any code optimization, and therefore you will see that there are many places to write code redundancy. tinyriscv processor core has the following characteristics:
1) to achieve a RV32I instruction set, the instruction compatibility testing by RV32I riscv, the following instructions: add addi and andi auipc beq bge bgeu blt bltu bne fence_i jal jalr lb lbu lh lhu lw lui or ori sb sh sw sll slli slt slti sltiu sltu sra srai srl srli sub xor xori;
2) using three lines, namely fetch, decode, fetch, execute, writeback;
3) can run simple c language program;
For details, see the source code and the cloud: https://gitee.com/liangkangnan/tinyriscv