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This week, I will sort out some of the frequently asked questions in the following IC design interviews: static timing analysis.
1. What is static timing analysis?
Static timing analysis is the workflow of predicting and calculating the timing of digital circuits.
Static timing analysis is generally performed in the process of synthesis, layout, and routing, mainly analyzing setup time and hold time.
Setup time Tsetup: the time the data needs to remain stable before the rising edge of the clock arrives;
Hold time Thold: the time the data needs to remain stable after the rising edge of the clock arrives;
Transmission time Tpd: After the rising edge of the clock arrives, the minimum time interval for data to pass from the input terminal to the output terminal.
Second, why static timing analysis?
If the circuit cannot meet the setup time and hold time, then the state of the circuit cannot be determined and enters a metastable state. We cannot determine the output of the circuit, nor can we determine when the circuit will stabilize to the correct level, so it can be seen that static timing analysis is very necessary.
Dig another hole here, and you can also think about it, why must the setup time and hold time be satisfied for the trigger to work properly? Or why are there such requirements as setup time and hold time?
In fact, this is determined by the internal circuit structure of the flip-flop, which will be explained in detail later.
3. How to perform static timing analysis?
Here we take DC as an example: Design Complier will automatically calculate whether there is a violation of the setup time and hold time in the circuit based on the circuit delay given by the process library and the timing constraints we artificially set, and give a margin.
DC will calculate data arrival time and data required time, slack (margin) is positive to indicate that the circuit can meet the requirements.
setup time slack = data arrival time - data required time
hold time slack = data required time - data arrival time
Therefore, we only need to give timing constraints during synthesis , and the software will automatically perform timing analysis. How to perform DC timing constraints can refer to the previous blog:
4. How to analyze the timing report?
After the DC completes the timing analysis, it will get a timing analysis report, so what does this report contain, and how should we analyze it?
1. The principle of timing analysis
timing path
A timing path is a point-to-point data path, and data is transmitted along the timing path. Each timing path has a starting point startpoint and an ending point endpoint . startpoint is defined as an input port or clock pin of a register or flip-flop, and endpoint is defined as an output port or an input pin of a register or flip-flop other than the clock pin.
Then, we can divide all timing paths into the following four types: input to register, register to register, register to output, input to output , as shown in the following figure:
In more detail: (note the specific port)
input -----> DFF_D
DFF_CLK -----> DFF_D
DFF_CLK -----> output
input -----> output
The path with the longest delay among all timing paths is called the critical path .
Timing Analysis Principle
Take the most common register-to-register timing path as an example for analysis:
Tclk1: the delay from the clock source (such as crystal oscillator) to the clock pin of flip-flop FF1;
Tclk2: Delay from clock source to flip-flop FF2 clock pin;
Tco: the time required for data to be transmitted from the flip-flop D pin to the Q pin;
Tlogic: Delay of combinational logic circuit;
Tsu: build time;
Tho: hold time;
T: clock period;
The analysis waveform diagram of setup time and hold time is as follows:
From the figure we can see that:
- for build time
data arrival time = Tclk1 + Tco + Tlogic
data required time = Tclk2 + T - Tsu
setup time slack = data required time - data arrival time
= T + (Tclk2 - Tclk1) - (Tco + Tlogic) - Tsu
Tclk2 - The larger the Tclk1, the larger the setup time margin.
- for hold time
data arrival time = Tclk1 + Tco + Tlogic
data required time = Tclk2 + Tho
hold time slack = data arrival time - data required time
= (Tco + Tlogic) - (Tclk2 - Tclk1) - Tho
Tclk2 - The larger the Tclk1, the smaller the hold time margin.
Only when the margins of the setup time and the hold time are greater than 0, we consider the circuit to be working normally. At the same time, it can also be clearly seen that the analysis of the hold time will be one clock cycle ahead of the setup time .
2. Analyze Timing Report
The following figure shows a timing report obtained after DC synthesis, which can be divided into two parts: basic information introduction + critical path timing.
- Basic Information
Basic situation of the report : timing indicates that this is a timing report, delay max indicates that it is a critical path, the path with the longest delay; the name of the design, the version of the DC software, and the time when the report was generated.
operating conditions, Library : fast indicates that the working status is relatively good for fast, and other common ones are slow and typical;
Wire Load Model Mode : top indicates that the mode of the wire load model is top mode, which adopts a relatively conservative estimation method; in addition, there are segment and enclosed. The schematic diagrams of the three modes are as follows:
A top-level module TOP contains a sub-module SUB, which contains two smaller sub-modules B1 and B2, and their line load models are 50*50, 40*40, 20*20 and 30 respectively *30. Now there is a connection across the two sub-modules B1 and B2, and it is in the sub-module SUB. Which type of line-loading model should be used for this connection?
mode = top is a relatively pessimistic way. The connection adopts the line-load model of the top-level module. Because the design scale of the top-level module is the largest, the line-load model is the most pessimistic, which is 50*50;
mode = enclosed is a less pessimistic way. The line-load model of the connection will choose the line-load model of the module that completely wraps the connection, that is, the sub-module SUB, 40*40.
mode = segment means to divide this connection according to the different modules where it is located, and each block adopts the wire-loaded model of the module where it is located, that is, 20*20, 30*30, 40*40.
- critical path timing
As shown in the figure, firstly, the startpoint and endpoint of the critical path are explained . The brackets will indicate whether the endpoint is a trigger or an input or output port. The startpoint and endpoint in the figure are triggers triggered by the rising edge of the clock.
The path group indicates which clock domain the path is under, the path type indicates whether the path analyzes the setup time or the hold time, max indicates the setup time, and min indicates the hold time.
wire load model, Library : a wire load model under a process library.
The entire critical path lists the data arrival time and data required time for analysis respectively, the point column indicates the name of the pin of the device that each step of the path reaches, incr indicates the delay of each small section of the path, and path indicates the current The total delay of the route traveled. Finally, slack gives the timing margin of the critical path. The margin is greater than or equal to 0 (MET) indicating that the path meets the timing requirements, and less than 0 (VOILATE) indicates a timing violation.
Summarize
The above is the content related to the static timing analysis learned today. Welcome everyone to discuss and exchange~
References:
Tcl and Design Compiler (6) - Basic Timing Path Constraints - IC_learner - Blog Park (cnblogs.com)
Tcl and Design Compiler (7) - Environment, Design Rules and Area Constraints - IC_learner - Blog Park (cnblogs.com)
Static timing analysis (the clearest version of the principle) - Zhihu (zhihu.com)