At present, as mobile devices such as mobile phones contain more and more sensors, the limitations of the I2C/SPI interface traditionally applied to sensors are becoming more and more obvious. The typical defects are as follows:
1. The increase of sensors and other devices has put forward more stringent requirements on the speed and power consumption of the control bus;
2. Although I2C is a one-to-two-wire interface, such devices often require an additional interrupt INT signal line;
In order to solve the above problems, the I3C interface bus and protocol were introduced. Let's take a look at the characteristics of the I3C bus.
1. Application scenarios of I3C
From the above image we can see:
1. The I3C bus can be used in various sensors;
2. It can be used in any traditional I2C/SPI/UART interface device.
2. What is I3C
I3C absorbs the key features of I2C and SPI and unifies them, while retaining the 2-wire serial interface structure on the basis of I2C, so that engineers can connect a large number of sensors in a single device.
From the above figure, we can specify the characteristics:
1. The I3C bus can support multi-master, that is, multi-master devices
2. The I3C bus is still compatible with traditional I2C devices
3, can support soft interrupt
4. Lower power consumption compared to I2C bus
5. Faster speed, can support up to 12.5MHZ
It can be seen from the figure below that there are too many I/0 ports in the traditional I2C interface device. After replacing it (I2C/SPI) with I3C, a large part of the signal line overhead can be saved. is also more convenient.
According to the current plan of the MIPI Alliance, the I3C bus will have the following application fields in addition to sensors in the future: camera, TP, etc.
3. I3C interface protocol
From the above figure, you can clearly see the application of the I3C bus. The I3C bus supports multi-master devices and is compatible with I2C.
The specific types of supported devices are:
1. I3C master device
-----SDR-only master
2、I3C secondary MASTER
-----SDR-only secondary master (note that it is slave of main master, that is, it is still a slave device compared to the master device)
3. I3C slave device
-----SDR only slave
4、I2C slave
The above picture shows the waveform of serial clk and data transmission of I3C, pay attention to the label below: the interface of SDA is an open-drain structure, while the interface of SCL is a push-pull structure!
Fourth, I3C features detailed introduction
1. SDR dynamic address allocation
---I3C can dynamically assign a 7-bit address to all I3C slave devices (Note: There will be two standardized characteristics registers and an internal 48-bit temporary ID in the I3C slave device to assist this process, specifically how to assist I don't know yet)
--- Still supports I2C's static address
2. In-band interruption of SDR
---In the state of "bus available (bus idle)", the slave device can issue a "START" request signal;
---When the master device receives the request signal, the master device sends a clock signal and drives the assigned address to the bus, and then the slave device responds to the address (to prevent understanding problems, the English description is as follows)
---If there are multiple slave devices responding to the interrupt at this time, the device with the lowest assigned address will win the arbitration
---Data payload (ie, mandatory data bits) can be used with in-band interrupts (??? I don't understand, fill in the pits later)
3. error detection and recovery methodology
--- Mainly for errors generated by master and slave (9 error types: parity, cyclic redundancy check CRC5)
4. Common command codes (common command codes)
