Digital audio interface - I2S bus protocol

        I2S (Inter-IC Sound) is a serial interface standard widely used in digital audio transmission. It was originally developed by Philips to solve the problem of transferring audio data between integrated circuits. The I2S protocol defines the transmission format, timing and control signals of audio data.

I2S signal definition

As shown above, the I2S interface is usually composed of three types of signal lines

• Clock line (Continuous Serial clock, SCK): The SCK line provides a clock signal for synchronous audio data transmission. It determines the speed and timing of data transfers. Also known as Bit Clock (BCLK).
• Left/right channel line (Word Select, WS): The WS line indicates whether the audio data of the left channel or the right channel is currently transmitted. It is also known as frame sync signal. Also called Frame Sync (FS), Word Clock (WCLK), Left-Right Clock (LRCLK).
• Data line (Serial Data, SD): The SD line is used to transmit actual audio data. The bit width of the data can vary depending on the specific application, usually 16 or 32 bits. Also known as Serial Data Out/In (SDOUT, SDIN)

The I2S protocol defines some parameters to describe the transmission method and format of audio data. The following are common parameters in the I2S protocol:

• Bit width (Word Length): The bit width specifies the number of bits of each sample data, usually 16 bits or 32 bits. Larger bit width can provide higher resolution and dynamic range.
• Clock Polarity: Clock polarity determines the clock edge on which data bits are transmitted. According to the specific I2S device and system settings, the rising or falling edge of the clock edge can be defined as the starting point of data transmission.
• Frame Sync Polarity: The frame sync polarity determines the active level of the frame sync signal. The frame sync signal indicates the frame start and end positions of the audio data. The polarity of the frame synchronization signal can be set according to specific requirements.
• Transmission format (Data Format): The transmission format defines how the audio data is encoded, such as PCM (Pulse Code Modulation) or compression encoding. The transfer format can also specify the order of the data, such as whether the left channel is transmitted first or the right channel is transmitted first.

master-slave mode

        The I2S working mode can be master mode (Master Mode) or slave mode (Slave Mode). In master mode, the master device is responsible for providing clock signal and frame synchronization signal to control the transmission of audio data. In slave mode, the slave device receives clock and frame synchronization signals from the master device, and receives or transmits audio data.

As shown above:

1. TRANSMITTER (transmitter) = CONTROLLER (controller): The transmitter plays the role of the master device in I2S communication. It is responsible for generating and transmitting audio data, controlling the timing of communication and clock signals. The transmitter controls data transmission by sending clock signals such as frame clock BCLK and word select clock LRCLK/WS. Therefore, the transmitter can be regarded as the master controller, responsible for directing the data transmission process.
2. RECEIVER (receiver) = CONTROLLER (controller): When the receiver acts as a controller, it works in master mode, responsible for receiving and processing audio data from the transmitter, and providing a clock signal for synchronization. When the receiver acts as a controller, it generates clock signals, including frame clock BCLK and word selection clock LRCLK/WS, and controls data reception and processing.
3. Independent CONTROLLER (controller): The additional controller plays the role of master control in the I2S communication system. It is responsible for coordinating data transmission and timing control between TRANSMITTER and RECEIVER. The controller generates clock signals (such as frame clock BCLK and word select clock LRCLK/WS).

data transfer mode

        In the I2S interface standard, in addition to the Philips standard mode, there are two transmission modes, Left Justified and Right Justified. Their differences are mainly reflected in the alignment of the data frame and the position of the synchronization signal.

standard mode

 I2S philips standard

        For I2S Philips standard mode, data transmission and synchronization are as follows:

• LRCLK (left and right channel selection signal, WS): The LRCLK signal is used to indicate whether the current data frame is the data of the left channel or the right channel. When LRCLK is logic 0, it means that the currently transmitted data is valid data of the left channel; when LRCLK is logic 1, it means that the currently transmitted data is valid data of the right channel.
• BCLK (bit clock): The BCLK signal is the clock signal for data transmission. The sender updates data on the falling edge of BCLK, and the receiver reads data on the rising edge of BCLK. The frequency of BCLK is usually a multiple of the sampling frequency and is used for synchronous data transmission.
• Data delay: The valid data sent is delayed by one clock cycle relative to the change edge of LRCLK (from 0 to 1 or from 1 to 0). That is to say, the change of data occurs in the next BCLK period after the change of LRCLK.
• Taken together, when the LRCLK signal changes, it indicates whether the currently transmitted data is the left channel or the right channel. The sender updates data when the falling edge of BCLK changes, and the receiver reads data when the rising edge of BCLK changes. This ensures data synchronization and correct sampling order.

left justified mode

Left Justified

For the left-justified standard (Left-Justified Standard), the meaning of the LRCLK signal is opposite to that of the Philips standard. Under the left-aligned standard, LRCLK being logic 1 means that the left channel data is transmitted, and LRCLK being logic 0 means that the right channel data is being transmitted.

• The MSB of the left channel data is valid on the first rising edge of SCK/BCLK (Bit Clock) after the rising edge of LRCLK.
• The MSB of the right channel data is valid on the first rising edge of SCK/BCLK after the falling edge of WS.
• The advantage of the left-aligned format is that it does not need to care about the word length of the left and right channel data. As long as the clock cycle of LRCLK is long enough, the left-aligned method can support the 16-32-bit word length format.

Right Justified

right justified mode

Similarly, for the Right-Justified Standard, the meaning of the LRCLK signal is reversed from the Philips standard. Under the right-aligned standard, LRCLK being logic 1 means that the left channel data is transmitted, and LRCLK being logic 0 means that the right channel data is being transmitted.

• The LSB of the left channel data is valid on the rising edge of SCK/BCLK before the falling edge of LRCLK.
• The LSB of the right channel data is valid on the rising edge of SCK/BCLK before the rising edge of LRCLK.
• Compared with the left-aligned format, the disadvantage of right-aligned format is that the receiving device must know the word length of the data to be transmitted in advance.