PCB Design Series Learning - High Speed ADC Layout and Routing Rules

To ensure design performance meets data sheet specifications, there are some guidelines that must be followed when using high-speed converters. First, a common question: "Should the AGND and DGND ground planes be separated?" The short answer is: it depends.
The detailed answer is: usually not separated. Because in most cases, splitting the ground plane will only increase the inductance of the return current, which will do more harm than good. From the formula V = L(di/dt), it can be seen that as the inductance increases, the voltage noise will increase. And as the switch current increases (because the converter sampling rate increases), the voltage noise also increases. Therefore, the ground planes should be tied together.
An example is that in some applications, dirty bus power or digital circuits must be placed in certain areas in order to comply with traditional design requirements, while also being affected by size constraints, which prevent the board from achieving good layout partitioning, in In this case, a split ground plane is key to good performance. However, for the overall design to be effective, there must be a bridge or connection point somewhere on the board to tie these ground planes together. Therefore, the connection points should be evenly distributed on the separated ground planes. Ultimately, there is often a connection point on the PCB that is the sweet spot for the return current to pass without degrading performance. This connection point is usually near or below the converter.

When designing power planes, use all the copper traces available to those planes. If possible, do not share traces between these layers, as the extra traces and vias can quickly damage the power plane by breaking it into smaller pieces. The resulting sparse power plane can squeeze the current paths to where they are needed most, the converter's power pins. Squeezing the current between the via and the trace increases the resistance, causing a slight voltage drop at the power pin of the converter.
Finally, the placement of the power planes is critical. Do not stack noisy digital power planes on top of analog power planes, as they may still couple even though they are on different layers. To minimize the risk of system performance degradation, the design should space these types of layers as much as possible rather than stack them together.

2.PDS design

Part 1 discusses why the AGND and DGND ground planes do not have to be separated unless the specifics of your design dictate that you do. This section discusses the design of power delivery systems (PDS) on printed circuit boards (PCBs), an often overlooked but critical task for system-level analog and digital designers.
The PDS is designed to minimize voltage ripple in response to supply current demands. All circuits require current, some more than others, and others at a faster rate. Using adequately decoupled low-impedance power or ground planes and good PCB stack-up minimizes voltage ripple due to the current demands of the circuit. For example, if the designed switch current is 1 and 4, the impedance of PDS is 10m0, then the maximum voltage ripple is 10mv.
First, a PCB stackup should be designed to support larger layer capacitances. For example, a six-layer stackup might contain a top signal layer. The first ground layer. The first power layer. Second power layer, second ground layer and bottom signal layer. It is specified that the first ground plane and the first power plane are close to each other in the stack structure, and the distance between these two layers is 2 to 3 mils, forming an inherent layer capacitance. The biggest advantage of this capacitor is that it is free, just note it in the PCB fabrication notes. If power planes must be split, with multiple VDD rails on the same layer, the largest possible power plane should be used. Do not leave voids, and be careful with sensitive circuitry. This will maximize the capacitance of this VDD plane. If the design allows for additional layers (in this case, going from six to eight layers), two additional ground planes should be placed between the first and second power planes. At the same 2 to 3 mil pitch between cores, the inherent capacitance of the stack is doubled.
For an ideal PCB stackup, decoupling capacitors should be used both at the start of the power plane entry point and around the DUT, which will ensure low PDS impedance across frequency. Using several 0.OO1uF to 100uF capacitors helps cover this range. There is no need to have capacitors everywhere; docking the capacitor right against the DUT breaks all manufacturing rules. If such drastic measures are required, something else is wrong with the circuit.

3. Exposed Pad Design

The exposed pad (pin 0) refers to a pad on the underside of most modern high-speed ICs, and it is an important connection through which all of the chip's internal grounds are connected to the center point under the device. The presence of the exposed pad allows many converters and amplifiers to omit the ground pin. The key is to form a stable and reliable electrical and thermal connection when soldering this pad to the PCB, otherwise the system could be severely damaged.
Optimal electrical and thermal connections to the exposed pad can be achieved by following three steps. First, where possible, the exposed pad should be replicated on each PCB layer. This will provide a thick thermal connection to all grounds, allowing for rapid heat dissipation, which is especially important for high power dissipation devices. Electrically, this will provide a good equipotential bonding for all ground planes. When the exposed pad is replicated on the bottom layer, it can be used as a decoupling ground point and as a place to mount a heat sink. Second, split the exposed pad into multiple identical sections. Best in a checkerboard pattern, this can be achieved with a wire mesh cross grid or a solder mask. During reflow assembly, there is no way to decide how the solder paste will flow to establish the connection of the device to the PCB, so the connections may be present but not evenly distributed, or worse, small and located in the corners. Dividing the exposed pad into smaller sections allows each area to have a connection point, ensuring a reliable, uniform connection between the device and the PCB.
Finally, you should make sure that each section has vias connected to ground. Each area is usually large enough to place multiple vias. It is important to fill each via with solder paste or epoxy prior to assembly to ensure that the exposed pad solder paste does not reflow into the via void, which reduces the chances of a proper connection.
For an ideal PCB stackup, decoupling capacitors should be used both at the start of the power plane entry point and around the DUT, which will ensure low PDS impedance across frequency. Using several 0.OO1uF to 100uF capacitors will help cover this range. There is no need to have capacitors everywhere; docking the capacitor right against the DUT breaks all manufacturing rules. If such drastic measures are required, something else is wrong with the circuit.

4. The problem of cross-coupling between layers

Select one of the adjacent layers and inject the signal at that layer. Then, connect the cross-coupling layer to a spectrum analyzer. It can be seen that there are a lot of signals coupled to adjacent layers. Even with a 4 mil spacing, adjacent layers in a sense still form a capacitance, so at certain frequencies, signals are still coupled from one layer to another. Assuming that the high-noise digital part on a certain layer has IV signals of high-speed switches, when the inter-layer isolation is 6OdB, the non-driven layer will see a 1mV signal coupled from the driven layer. For a 12-bit analog-to-digital converter (ADC) with a full-scale swing of 2Vp-p, this means 2LSB (least significant bit) coupling. For a particular system, this may not be a problem, but it should be noted that when the resolution is increased from 12 bits to 4 bits, the sensitivity will increase by a factor of four. Thus the error will increase to 8LSB.
Ignoring cross-plane/cross-layer coupling may not cause the system design to fail, or weaken the design, but one must be vigilant because there may be more coupling between the two layers than imagined.
This should be taken into account when noise spurious coupling is found within the frequency spectrum of interest. Sometimes placement and routing can cause unintended signal or layer cross-coupling to different layers. Keep this in mind when debugging sensitive systems: the problem may lie one layer below.
For an ideal PCB stackup, decoupling capacitors should be used both at the start of the power plane entry point and around the DUT, which will ensure low PDS impedance across frequency. Using several 0.OO1uF to 100uF capacitors will help cover this range. There is no need to have capacitors everywhere; docking the capacitor right against the DUT breaks all manufacturing rules. If such drastic measures are required, something else is wrong with the circuit.

summary

This article mainly shares the layout and routing rules of high-speed ADC design from various aspects.