overview
A good layout design can optimize efficiency and reduce thermal stress. And minimize the noise and effects between traces and components. It all starts with the designer's understanding of the current conduction paths and signal flow in the power supply.
When a prototype power strip is first powered up, the best case scenario is that it not only works, but is also quiet. Low fever. However, this situation is rare.
A common problem with switching power supplies is "erratic" switching waveforms. Sometimes, the waveform jitter is in the acoustic range. Magnetic components can generate audible noise. If the problem lies in the layout of the printed circuit board. Finding out why can be difficult. Therefore, the correct PCB layout at the initial stage of switching power supply design is very critical.
overall architecture process
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For example:
In the language model, the encoder and decoder are formed by splicing Transformer components one by one.
Explanation of technical terms
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technical details
1. Layout rules
Embedded dcldc power supply on a large circuit board. To get the best voltage regulation. Load transient response and system efficiency require the power supply output to be close to the load device. Minimize interconnect impedance and conduction voltage drop on PCB traces. Make sure there is good air flow. Limit thermal stress; if forced air cooling can be used. Place the power supply close to the fan.
in addition. Large passive components (such as inductors and electrolytic capacitors) must not block the airflow through the low-profile surface-mount semiconductor components. Such as power MOSFET or PWM controller. To prevent switching noise from interfering with the analog signals in the system, avoid routing sensitive signal lines under the power supply as much as possible: otherwise, an internal ground plane between the power plane and the small-signal plane is required for shielding.
The key is in the early design and planning stages of the system. Just plan the location of the power supply. and the need for board space. Designers sometimes ignore this advice and focus on the more "important" or "exciting" circuits on large system boards. Space-wise, this approach is very detrimental to an efficient and reliable power supply design.
For multilayer boards. A good method is to place a DC ground or DC input/output voltage layer between the high-current power component layer and the sensitive small-signal trace layer. The ground plane or DC voltage plane provides an AC ground that shields small-signal traces from interference from high-noise power traces and power components.
As a general rule, neither the ground plane nor the DC voltage plane of a multilayer PCB should be separated. If this separation is unavoidable. It is necessary to minimize the number and length of the traces on these layers, and the layout of the traces should be kept in the same direction as the large current to minimize the impact.
2. Power Stage Layout
The switching power supply circuit can be divided into two parts: power circuit and small signal control circuit. Power stage circuits contain components used to transmit large currents, usually. To place these components first. Then place small-signal control circuits at specific points in the layout.
High current traces should be short and wide. Minimize the inductance of the PCB. resistance and voltage drop. For those traces with high di/dt pulse current. This aspect is especially important.
The continuous current path and pulse current path in a synchronous buck converter are given, and the solid line represents the continuous current path. The dashed line represents the pulse (switch) current path. The pulse current path includes the traces connected to the following components: input decoupling ceramic capacitor C:: upper control FETOr; and lower synchronous FETOa and optional parallel Schottky diode.
The PCB parasitic inductance in the high dildt current path is given. Due to the existence of parasitic inductance, the pulse current path will not only radiate the magnetic field. And it creates large voltage ringing and spikes on PCB traces and MOSFETs. In order to minimize the PCB inductance, the pulse current loop (so-called hot loop) should have the smallest circumference when laying out, and its trace should be short and wide.
The high-frequency decoupling capacitor Cur should be 0.1uF~10uF, ceramic capacitor with X5R or X7R dielectric, it has extremely low ESL (effective series inductance and ESR (equivalent series resistance). Larger capacitor dielectric "(such as Y5V) May cause a large drop in capacitance value at different voltages and temperatures, so not the best material for C:r
An example layout is provided for the critical pulsed current loop in a buck converter. In order to limit the resistance voltage drop and the number of vias. The power components are all placed on the same side of the board, and the power traces are all placed on the same layer. When it is necessary to route a power line to another layer, select a trace that is in the continuous current path. When using vias to connect PCB layers in high current loops, use multiple vias to minimize impedance.
Shown are continuous and pulsed current loops in a boost converter. At this time, a high-frequency ceramic capacitor CHF should be placed near the output of MOSFETOa and boost diode D.
An example layout of a pulsed current loop in a boost converter. At this point the key is to minimize the switching tube Qa. The loop formed by the rectifier diode D and the high frequency output capacitor CHr. Figure 6 and Figure 7 (omitted) provide an example of a synchronous buck circuit, which emphasizes the importance of decoupling capacitors. Figure 6a is a dual-phase 12Vw2.Vou/30A (maximum value) synchronous step-down power supply, using the LTC3729 dual-phase single Vor controller 1C. When there is no load, the waveforms of the switching nodes SW1 and SW2 and the output inductor current are stable. But if the load current exceeds 13A, the waveform at the SWI node starts to lose cycles. The problem is exacerbated at higher load currents.
Adding two 1uF high-frequency ceramic capacitors at the input of each channel can solve this problem. The capacitors isolate the hot loop area of each channel. and minimize it. Even at a maximum load current of up to 30A. The switching waveform is still very stable.
3. High DV/DT layout
The SW voltage swing between Vw (or Vour) and ground has a high dvldt rate. This junction is rich in high frequency noise components and is a strong source of EM noise. To minimize the coupling capacitance between the switch node and other noise-sensitive traces, you may want to keep the SW copper area as small as possible. However, in order to conduct a large inductor current. And provide a heat dissipation area for the power MOSFET tube, and the PCB area of the SW node cannot be too small. It is generally recommended to lay out a ground copper foil area under the switch node. Provides additional shielding.
summary
The current level and noise sensitivity are unique to a specific controller pin. Therefore, specific trace widths must be chosen for different signals. Usually, the small-signal network can be narrower. Use traces with a width of 10mil-15mil. The large current network <gate drive. Ve and, PGND should use short and wide traces. The traces of these networks are recommended to be at least 20mil wide.