Digital circuits often require discontinuous current, so some high-speed devices will generate inrush current. If the power supply trace is very long, the presence of inrush current will cause high-frequency noise, and this high-frequency noise will be introduced into other signals. In high-speed circuits, there must be parasitic inductance, parasitic resistance, and parasitic capacitance, so the high-frequency noise will eventually be coupled to other circuits, and the existence of parasitic inductance will also lead to the maximum surge current that the wiring can withstand. drop, resulting in a partial voltage drop that may disable the circuit. So it is particularly important to add a bypass capacitor in front of the digital device. The larger the capacitance, the energy transmission is limited by the transmission rate, so a large capacitor and a small capacitor are generally combined to meet the full frequency range.
Avoid hot spots: signal vias will generate voids on the power layer and bottom layer. Therefore, unreasonable placement of vias is likely to increase the current density in certain areas of the power supply or ground plane. And these places where the current density increases are called hot spots.
Therefore, we must try our best to avoid this situation when setting via holes, so as to avoid the plane being split, which will eventually lead to EMC problems. Usually the best way to avoid hot spots is to place vias in a mesh pattern, so that the current density is uniform, and the planes will not be isolated, the return path will not be too long, and there will be no EMC problems.
02
The bending method of the trace
When laying high-speed signal lines, the signal lines should try to avoid bending. If you have to bend traces, do not trace at acute or right angles, but at obtuse angles.
When laying high-speed signal lines, we often achieve equal length by running serpentine lines. The same serpentine line is actually a kind of bending of the wiring. The line width, spacing, and bending method should be reasonably selected, and the spacing should meet the 4W/1.5W rule.
03
signal proximity
If the distance between high-speed signal lines is too close, it is easy to generate crosstalk. Sometimes, due to the layout, frame size and other reasons, the distance between the high-speed signal lines we lay out exceeds our minimum required distance, so we can only increase the distance between the high-speed signal lines as much as possible near the bottleneck. distance. In fact, if the space is enough, try to increase the distance between the two high-speed signal lines.
04
Wire stubs
A long stub cable is equivalent to an antenna, and improper handling will cause serious EMC problems. At the same time, the stub line will also cause reflections and reduce the integrity of the signal. Usually, when a pull-up or pull-down resistor is added to a high-speed signal line, a stub line is most likely to be generated, and the general routing of the stub line can be chrysanthemum routing. According to experience, if the length of the stub line is greater than 1/10 wavelength, it can be used as an antenna, and it will become a problem at this time.
05
impedance discontinuity
The impedance value of a trace generally depends on its width and the distance between the trace and the reference plane. The wider the trace, the lower its impedance. The principle is also applicable to some interface terminals or pads of devices. When the pad of an interface terminal is connected to a high-speed signal line, if the pad is particularly large at this time, and the high-speed signal line is particularly narrow, the impedance of the large pad is small, and the narrow trace must have a large impedance. In this case, there will be impedance discontinuity, and the impedance discontinuity will cause signal reflection. Therefore, in general, in order to solve this problem, a forbidden copper sheet is placed under the large pad of the interface terminal or device, and the reference plane of the pad is placed on another layer to increase the impedance and make the impedance continuous.
Vias are another source of impedance discontinuities. To minimize this effect, unwanted copper on inner layers and via connections should be removed. In fact, such an operation can be eliminated through CAD tools or contacted with the PCB processing manufacturer during design to eliminate unnecessary copper skin and ensure the continuity of impedance.
06
differential signal
For high-speed differential signal lines, we must ensure equal width and equal spacing to achieve a specific differential impedance value. Therefore, try to ensure symmetry when laying out the differential signal lines.
It is forbidden to arrange vias or components in the differential line pair. If vias or devices are placed in the differential line pair, EMC problems will occur and impedance discontinuity will also occur.
Sometimes, some high-speed differential signal lines need to be connected in series with coupling capacitors. The coupling capacitors also need to be arranged symmetrically, and at the same time, the packaging of the coupling capacitors cannot be too large.
Usually, vias will produce a huge impedance discontinuity, so for high-speed differential signal line pairs, minimize vias, and arrange symmetrically if vias are to be used.
07
Isometric problem
In some high-speed signal interfaces, such as buses, etc., it is necessary to consider the arrival time and skew error between the signal lines. For example, the arrival time of all data signal lines in a group of high-speed parallel buses must be within a certain time lag error to ensure the consistency of their setup time and hold time. In order to meet this requirement, we have to consider equal lengths.
The high-speed differential signal line must ensure a strict time lag between the two signal lines, otherwise the communication may fail. Therefore, in order to meet this requirement, equal lengths can be realized through serpentine lines, thereby satisfying the time-lag requirement.
Serpentine lines should generally be placed at the source of the loss of length, not at the far end. Only at the source can the signals at the positive and negative ends of the differential line be transmitted synchronously most of the time.
Trace bends are one of the sources of loss of length. For the bend of the trace, the equal length should be close to the bend (<=15mm)
If there are two traces bent, and the distance between them is <15mm, the length loss of the two will compensate each other at this time, so there is no need to do equal length processing at this time.
For the high-speed differential signal lines in different parts, they should be independent and equal in length. Vias, series coupling capacitors and interface terminals will be divided into two parts by high-speed differential signal lines, so special attention should be paid at this time. They must be equal in length. Because many EDA software only pay attention to whether the entire trace is out of length during DRC.
For interfaces such as LVDS display devices, there will be several pairs of differential pairs at the same time, and the timing requirements between differential pairs are generally very strict, and the time lag requirements are particularly small. Therefore, for such differential signal pairs, we generally require that they be in the same plane. Make compensation. Because the signal transmission speed of different layers is different.
When some EDA software calculates the length of the trace, the trace inside the pad will also be included in the length. If the length compensation is performed at this time, the final actual result will be lost. So pay special attention at this time, when using some EDA software.
At any time, if you can, you must choose symmetrical outlets to avoid the need for final serpentine routing for equal lengths.
If space permits, try to add a small loop at the source of the short differential line to achieve compensation instead of compensating through the serpentine line.
