Table of contents
Explanation of technical terms
3. Decoupling and Layer Capacitance
overview
In today's industrial world, system board layout has become an integral part of the design itself. Therefore, design engineers must understand the mechanisms that affect the performance of high-speed signal chain designs.
overall architecture process
In high-speed analog signal chain design, printed circuit board (PCB) layout requires consideration of many options, some more important than others, and some depending on the application. The final answer varies, but in all cases, designers should try to eliminate best practice errors rather than dwelling on every detail of placement and routing. This application note provides information to help design engineers with their next high-speed design project.
Explanation of technical terms
PCB: PCB (Printed Circuit Board), the Chinese name is printed circuit board, also known as printed circuit board, is an important electronic component, a support for electronic components , and a carrier for electrical interconnection of electronic components . Because it is made using electronic printing, it is called a "printed" circuit board
technical details
1. Exposed Pad
The exposed pad, which Analog Devices calls pin 0, is the pad underneath most devices today. It is an important connection through which all internal grounds of the chip are connected to the center point under the device. In case you noticed, the reason for the lack of a ground pin in many converters and amplifiers today is the exposed pad.
The key is to secure (i.e. solder) this pin to the PCB for a solid electrical and thermal connection. If this connection is not strong, chaos will ensue, in other words, the design may not work.
2. Optimal connection
There are three steps to achieving the best electrical and thermal connection with the exposed pad. First, where possible, the exposed pad should be replicated on each PCB layer to allow for a dense thermal connection to all grounds and ground planes for rapid heat dissipation. This step is relevant for high power devices and applications with high channel counts. Electrically, this will provide a good equipotential bonding for all ground planes.
It is even possible to replicate the exposed pad on the bottom layer (see Figure 1), which can be used as a thermal ground point for decoupling and as a place to mount a bottom-side heatsink.
3. Decoupling and Layer Capacitance
Sometimes engineers ignore the purpose of using decoupling and just spread out many resistors of different sizes on the board, so that the lower impedance power supply is connected to ground. But the question remains: how many resistors are needed? Much of the literature suggests that many resistors of varying sizes must be used to reduce the impedance of a power delivery system (PDS), but this is not entirely true. Instead, the PDS impedance can be lowered simply by selecting the correct size and the correct type of resistor.
For example, consider designing a 10mQ reference layer, as shown in Fig. As the red curve shows, many different values of resistors are used on the system board, 0.001uF. 0.01uF. 0.1uF and so on. This can of course lower the impedance in the 5O0MHz frequency range, however, see the green curve, the same design uses only 0.1uF and 10pF resistors. This proves that if you use the correct capacitors, you don't need so many resistors. This also helps save space and bill of material (BOM) costs.
Note that not all electrics are "created equal", even if the same supplier, there are differences in craftsmanship, size and style. If the correct capacitors are not used, either multiple capacitors or several different types, can have adverse effects on the PDS.
The result may be an inductive loop. Improperly placed capacitors or resistors of different make and model (and thus respond differently to frequencies within the system) can resonate with each other.
4. High-frequency layer capacitance of PDS
To design a qualified PDS, it is necessary to use a variety of electronics [see Figure 4]. Typical voltage values used on a PCB will only reduce the impedance from DC or near DC frequencies to about 500MHz range. At frequencies above 500MHz, the charge depends on the internal capacitance formed by the PCB. Note that close stacking of power and ground planes helps.
A PCB stackup should be designed to support larger layer capacitances. For example, a six-layer stackup might contain a top signal layer. The first ground layer. The first power layer. The second power layer. Second ground plane and bottom signal layer. Provision is made for the first ground plane and the first power plane to be close to each other in the stackup, with a spacing of 2 to zimil between these two layers, forming an inherent high frequency plane capacitance. The biggest worry about this capacitor is that it's free, just note it in the PCB fabrication notes. If power planes must be split, with multiple VDD rails on the same layer, the largest possible power plane should be used. Do not leave voids, while taking care of sensitive circuits. This will maximize the capacitance of this VDD plane.
If the design allows for additional layers [in the example above, going from six to eight layers], then two additional ground planes should be placed between the first and second power planes. In the case that the core spacing is also 2 to 1 mil, the stacked structure at this time
5. Separate ground
The question most often asked by analog signal chain designers is: Should the ground plane be split into AGND and DGND ground planes when using an ADC? The short answer is: it depends.
The detailed answer is : usually not separated . Why not? Because in most cases, blindly separating the ground plane will only increase the inductance of the return path, and it will do more harm than good.
From the formula V=L (di/dt), it can be seen that as the inductance increases, the voltage noise will increase. As the inductance increases, the impedance of the PDS, which designers have been working so hard to keep down, also increases. As the need to increase ADC sampling rates continues to grow, there are limited ways to reduce switch current (disdt). So keep those ground connections unless you need to separate the ground planes.
summary
on the evaluation board. At the module and system level, a simple single ground is best. Good circuit partitioning is key. This also affects layer and adjacent layer layout. Be aware that cross-coupling may occur if sensitive layers are above noisy digital layers. Assembly is also important; manufacturing notes provided to the PCB shop or assembly shop should be put to good use to ensure a reliable connection between the IC exposed pad and the PCB.
Poor assembly often results in poor system performance. Decoupling close to the power plane entry point and VDD pin of the converter or IC is always beneficial.
However, to increase the inherent high-frequency decoupling circuit, closely stacked power and ground planes should be used. This method incurs no additional cost and only takes a few minutes to update the PCB fabrication notes. Design high speed. When laying out a high-resolution converter, it is difficult to take care of all the specific features. Every app is unique. Hopefully, the few points covered in this application note will help design engineers better understand future system designs.