PCB Modular Design 12——LVDS High Speed PCB Layout and Routing Design Specifications

PCB Modular Design 12——LVDS High Speed ​​PCB Layout and Routing Design Specifications

1. Introduction to LVDS

LVDS (Low Voltage Differential Signaling) is a high-speed digital interface that has become the solution for many applications that require low power consumption and high noise immunity for high data rates. LVDS has been implemented in various applications and industries since the standardization of ANSI/TIA/EIA-644. The LVDS standard provides guidelines for defining the electrical characteristics of the driver output and receiver input of the LVDS interface, but does not define a specific communication protocol, so required process technology, medium or voltage supply. The general non-application nature of the standard facilitates the adoption of LVDS in a variety of commercial and military applications. Additionally, ever-increasing bandwidth demands have led to the emergence of high-performance technologies such as PCI Express and HyperTransport, which are based on high-speed LVDS connections. The low power consumption and high noise immunity of LVDS coupled with the large availability of commercial off-the-shelf (COTS) LVDS components has led many military and aerospace applications to choose LVDS as a robust, long-term solution for high-speed data transmission.

2. LVDS conventional interface definition

Although we will see many kinds of LVDS interfaces in the application of products, the real definitions are divided into the following categories:

20PIN single 6 definitions:

1: Power 2: Power 3: Ground 4: Ground 5: R0- 6: R0+ 7: Ground 8: R1- 9: R1+ 10: Ground 11: R2- 12: R2+ 13: Ground 14: CLK- 15: CLK+ 16 Empty 17 Empty 18 Empty 19 Empty 20 Empty

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

20PIN double 6 definition:

1: Power 2: Power 3: Ground 4: Ground 5: R0- 6: R0+ 7: R1- 8: R1+ 9: R2- 10: R2+ 11: CLK- 12: CLK+ 13: RO1- 14: RO1+ 15: RO2 - 16: RO2+ 17: RO3- 18: RO3+

19：CLK1- 20：CLK1+

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

20PIN single 8 definition:

1: Power 2: Power 3: Ground 4: Ground 5: R0- 6: R0+ 7: Ground 8: R1- 9: R1+ 10: Ground 11: R2- 12: R2+ 13: Ground 14: CLK- 15: CLK+ 16 : R3- 17: R3+

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

30PIN single 6 definitions:

1: Empty 2: Power 3: Power 4: Empty 5: Empty 6: Empty 7: Empty 8: R0- 9: R0+ 10: Ground 11: R1- 12: R1+ 13: Ground 14: R2- 15: R2+ 16: Land 17: CLK- 18: CLK+ 19: Land 20: Empty- 21: Empty 22: Empty 23: Empty 24: Empty 25: Empty 26: Empty 27: Empty 28 Empty 29 Empty 30 Empty

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

30PIN single 8 definition:

1: Empty 2: Power 3: Power 4: Empty 5: Empty 6: Empty 7: Empty 8: R0- 9: R0+ 10: Ground 11: R1- 12: R1+ 13: Ground 14: R2- 15: R2+ 16: Ground 17: CLK- 18: CLK+ 19: Ground 20: R3- 21: R3+ 22: Ground 23: Empty 24: Empty 25: Empty 26: Empty 27: Empty 28 Empty 29 Empty 30 Empty

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

30PIN double 6 definition:

1: Power 2: Power 3: Ground 4: Ground 5: R0- 6: R0+ 7: Ground 8: R1- 9: R1+ 10: Ground 11: R2- 12: R2+ 13: Ground 14: CLK- 15: CLK+ 16 : Ground 17: RS0- 18: RS0+ 19: Ground 20: RS1- 21: RS1+ 22: Ground 23: RS2- 24: RS2+ 25: Ground 26: CLK2- 27: CLK2+

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

30PIN double 8 definition:

1: Power 2: Power 3: Power 4: Empty 5: Empty 6: Empty 7: Ground 8: R0- 9: R0+ 10: R1- 11: R1+ 12: R2- 13: R2+ 14: Ground 15: CLK- 16 : CLK+ 17: Ground 18: R3- 19: R3+ 20: RB0-21: RB0+ 22: RB1- 23: RB1+ 24: Ground 25: RB2- 26: RB2+ 27: CLK2- 28: CLK2+ 29: RB3- 30: RB3+

The resistance between each group of signal lines is (about 120 ohms on the digital meter)

Generally, 14PIN, 20PIN, and 30PIN are LVDS interfaces.

3. What are the main advantages of LVDS?

1. High-speed transmission capability and low swing: 350mv

The constant current source mode low swing output of LVDS technology means that LVDS can be driven at high speed, for example: for point-to-point connections, the transmission rate can reach 800Mbit/s.

It takes time to change from a logic "0" level to a logic "1" level. Since the physical level of the LVDS signal changes between 0.85-1.55V, the time it changes from a series "0" level to a logic "1" level is much faster than that of a TTL level.

2. Low noise/low electromagnetic interference

LVDS signals are low voltage differential signals. We know that differential data transmission is more resistant to common-mode input noise than single-line data transmission. On two differential signal lines, the direction of current and voltage amplitude are opposite, and the receiver only cares about the difference between the two signals. Therefore, when the noise is coupled to the two lines at the same time in a common mode, it can be canceled out, and the electromagnetic fields around the two signal lines also cancel each other out. Therefore, the electromagnetic radiation of the two differential signal lines is much smaller than that of the TTL single-line signal transmission. Moreover, the constant current source drive mode is less prone to ringing and switching spikes, further reducing noise.

3. Low power consumption

LVDS devices are generally implemented with CMOS technology, so they have lower static power consumption. The load (100Q termination resistor) of LVDS consumes only 1.2mW. LVDS adopts constant current source mode drive design, which greatly reduces the impact of frequency components on power consumption.

4. Low voltage

The LVDS interface adopts low-voltage differential signal technology, and its transmission and reception do not depend on the power supply voltage, such as 5V. Therefore, LVDS can be easily applied to low-voltage systems, such as 3.3V or even 2.5V, and maintain the same signal level and performance .

LVDS is also easy to terminate and match. Generally, a 100Ω matching resistor as close as possible to the receiving input terminal across the differential line can provide good matching and the best signal quality.

The distance between the 100 ohm resistor and the receiving end should not exceed 500mil, preferably within 300mil.

4. Common guidelines for LVDS layout

1. Impedance consistency

The differential signal (lvds) handled by afe requires impedance conformance (with gnd).

50 ohms (single-ended) 5% is recommended for the characteristic impedance in differential signaling mode.

Impedance conformance is typically achieved by matching impedance between differential signal patterns, p/n, and the test pattern created beneath them. As a result, the impedance of a differential signaling pattern may become inconsistent (discontinuous) by adjacent patterns (such as signal or gnd shields) or beta patterns located below the differential signaling pattern. Routing the same length through holes or gaps will result in inconsistencies.

In order to maintain the consistency of impedance, the following size requirements should be met. The choice of the gap between fixed potential adjacent boundaries (g2) or the gap between fluctuating potential adjacent boundaries (g3) depends on the adjacent pattern type. A fixed potential adjacency refers to the power supply or GND, while a fluctuating potential adjacency refers to a power supply circuit that shows signal patterns or high frequency components (such as close to the power supply circuit).

w: width of the differential signal pattern

g1: Gap between differential signaling modes

g2: fixed gap between potential adjacent boundaries

g3: Gap between potential adjacent boundaries of fluctuations [size required]

・In > g1

・g2 = 2xw (in > g1)

・g3 = 3xw (in > g1)

2. Bypass capacitor placement method

Since the bypass capacitor is responsible for supplying the effective current, it is necessary to know the following so that your design can achieve stable behavior of the bypass capacitor.

(1) The current path depends on the location of the via (via). This means that improper placement of vias can disable the function of bypassing capacitors.

(2) The distance between the capacitor and the pin may not only disable the function of the bypass capacitor, but also make the function of the bypass capacitor invalid and cause its deterioration.

In the example shown below, c2's current path takes precedence over c1, which is farther away from the pin. Internal circuits connected to C1 and between VCC1 and T to VCC2 may exhibit typical deterioration due to unexpected current flow.

3. Multi-layer board layout

Printed boards with LVDS signals are generally laid out as multi-layer boards. Since the LVDS signal is a high-speed signal, the layer adjacent to it should be the ground layer to shield the LVDS signal to prevent interference. In addition, for boards with a low density, it is best to place LVDS signals and other signals on different layers if the physical space conditions permit. For example, for a four-layer board, the layers can usually be laid out as follows: LVDS signal layer, ground layer, power layer, and other signal layers.

5. LVDS Signal Routing Design Guidelines

1. LVDS signal impedance calculation and control:

The voltage swing of the LVDS signal is only 350 mV, which is suitable for the differential signal mode driven by the current. In order to ensure that the signal is not affected by the reflected signal when propagating in the transmission line, the LVDS signal requires the impedance of the transmission line to be controlled, usually the differential impedance is (100±10)Ω. The quality of impedance control directly affects signal integrity and delay. How to control its impedance?

①. Determine the routing mode, parameters and impedance calculation. LVDS is divided into two types: the outer microstrip line differential mode and the inner strip line differential mode, as shown in Figure 2 and Figure 3 respectively. By setting parameters reasonably, the impedance can be calculated using relevant impedance calculation software (such as POLAR-SI6000, CADENCE's ALLEGRO) or the impedance calculation formula.

(i) Microstrip (microstrip)

Z={87/[sqrt(εr+1.41)]}ln[5.98H/(0.8W+T)]

Among them, W is the line width, T is the copper thickness of the trace, H is the distance to the reference plane, and εr is the dielectric constant (dielectric Constant) of the PCB material. This formula can only be applied when 0.1<(W/H)<2.0 and 1<(εr)<15.

(ii) Stripline (stripline)

Z=[60/sqrt(εr)]ln{4H/[0.67π(T+0.8W)]}

Among them, H is the distance between two reference planes, and the trace is located in the middle of the reference planes. This formula is suitable for double lines, and the line spacing is proportional to the resistance, and it must be applied when W/H<0.35 and T/H<0.25.

It can be seen from the above two formulas that although the calculation formulas are different, the impedance value is proportional to the thickness of the insulating layer and inversely proportional to the dielectric constant, line thickness and width.

②. LVDS wiring requires strict equal length, but it is recommended to pay attention to controlling the equal length as much as possible. The higher the resolution of the screen, the more it is necessary to control the equal length. For the 720P screen, it is recommended that the length difference between the lines should not exceed 1000MIL.

2. Tight coupling principle:

When calculating the line width and spacing, it is best to follow the principle of tight coupling, that is, the differential pair line spacing is less than or equal to the line width. When the distance between two differential signal lines is very close, the current transmission direction is opposite, the magnetic fields cancel each other, the electric fields couple with each other, and the electromagnetic radiation is much smaller.

3. Go short-term and straight-line:

In order to ensure the quality of the signal, the LVDS differential pair wiring should be as short and straight as possible, reduce the number of vias in the wiring, avoid too long differential pair wiring, and too many turns. Try to use 45° or arcs at the corners. Avoid 90° turns.

4. Processing between different differential line pairs:

LVDS has no restrictions on the choice of routing methods, both microstrip and striplines are acceptable, but care must be taken to have a good reference plane. The spacing between different differential lines requires that the spacing should not be too small, and should be at least 3 to 5 times greater than the spacing of differential lines. If necessary, add ground holes between different differential pairs to prevent mutual crosstalk.

5. LVDS signal is far away from other signals:

For LVDS signals and other signals such as TTL signals, it is better to use different wiring layers. If the same layer of wiring must be used due to design restrictions, the distance between LVDS and TTL should be far enough, at least 3 to 5 times greater than the differential line spacing.

6. LVDS differential signals cannot be divided across planes:

Although the two differential signals are return paths for each other, the cross-segmentation will not cut off the return flow of the signal, but the transmission line across the split part will cause impedance discontinuity due to the lack of a reference plane (as shown by the arrow in Figure 5, where GND1 and GND2 are ground plane adjacent to LVDS)

7. The layout of the matching resistor at the receiving end:

The distance from the matching resistor at the receiving end to the receiving pin should be as close as possible.

8. Accuracy requirements for matching resistors:

For point-to-point topology, the impedance of the trace is usually controlled at 100Ω, but the matching resistance can be adjusted according to the actual situation. The accuracy of the resistance is preferably 1% to 2%. Because as a rule of thumb, 10% impedance mismatch will produce 5% reflection.
Schematic reference display

 参考一（三星S5PV210）：

Reference 2 (Rockchip RK3288):

PCB case display

       一、液晶驱动板卡

2. Main board of advertising machine