As shown in the table below, the interface signal can work at a rate of 8Gbps and above. Due to the high rate, the requirements for PCB layout design will be more stringent. Based on the content of PCB layout in the previous articles, it is also necessary to follow the requirements of this article. PCB layout design.
When wiring high-speed signals, drill holes and change layers as little as possible, and choose the layer with GND on both sides for layer change. Try to route the sending and receiving signals on different layers. If the space is limited and the sending and receiving signals need to be routed on the same layer, the wiring distance between the sending and receiving signals should be increased.
For the above high-speed signals, there are also the following requirements:
01
Dig the reference layer in the BGA pad area
If the working rate of the interface is ≥ 8Gbps, it is recommended to dig out the L2 layer reference layer directly below these signals in the BGA area to reduce the capacitive effect of the pad, and the hollow size R=10mil.
If the working rate of the interface is less than 8Gbps, for example, the DP interface only works at 5.4Gbps, then there is no need to dig the reference layer of the BGA area, as shown in the figure below.
02
Avoid fiberglass weave effect
The PCB substrate is made of glass fiber and epoxy resin filled and laminated. The dielectric constant of glass fiber is about 6, and the dielectric constant of resin is generally less than 3. The problems with path length and signal speed are mainly caused by the glass fiber reinforced weave in the resin.
The glass fiber bundles in the more common glass fiber weaving are tightly twisted together, so a large number of gaps between the bundles need to be filled with resin, and the average conductor width in the PCB is smaller than the distance between the glass fibers, so a One wire in a differential pair may have more fiberglass and less resin, and the other wire does the opposite (more resin than fiberglass). This will cause the characteristic impedance of the D+ and D- traces to be different, and the delay of the two traces will also be different, resulting in a delay difference within the differential pair and affecting the quality of the eye diagram.
When the signal rate of the interface reaches 8Gbps, and the trace length exceeds 1.5inch, it is necessary to carefully handle the glass fiber weaving effect. It is recommended to use one of the following methods to avoid the influence of glass fiber weaving effect.
Method 1: Change the wiring angle, such as 10°~35°, or rotate the board by 10° during PCB production and processing to ensure that all wiring is not parallel to the glass fiber, as shown in the figure below.
Method 2: Use the wiring shown in the figure below, then W must be at least 3 times larger than the glass fiber braiding pitch, the recommended value is W=60mil, θ=10°, L=340mil.
03
Differential Via Recommendations
1. The high-speed signal should be drilled as little as possible to change the layer. When changing the layer, it is necessary to add a GND via hole next to the signal hole. The impact of the number of ground vias on the signal integrity of differential signals is different. No ground via, single ground via, and double ground via can sequentially improve the signal integrity of the differential signal.
2. Choose a reasonable via size. For multi-layer PCB design with general density, it is better to use 0.25mm/0.51mm/0.91mm (drill hole/pad/POWER isolation area) vias; for some high-density PCBs, 0.20mm/0.46mm can also be used mm/0.86mm vias, you can also try the blind buried via design.
3. The change of the center distance of the via hole has a different impact on the signal integrity of the differential signal. For differential signals, too large or too small center-to-center distance of vias will adversely affect signal integrity.
4. If the working rate of the interface is ≥ 8Gbps, then the via size of the differential pair of these interfaces is recommended to be simulated and optimized according to the actual stacking.
The reference dimensions of the vias based on the EVB first-order HDI stack are given below:
R_Drill=0.1mm (drilling radius)
R_Pad=0.2mm (via pad radius)
D1: Center-to-center spacing of differential vias
D2: The anti-pad size from the surface layer to the bottom layer
D3: The center distance between the signal via hole and the return ground via hole
04
Coupling Capacitor Optimization Recommendations
1. Place the coupling capacitor in accordance with the requirements of the design guidelines. If there is no design guide, if the signal is from IC to IC, the coupling capacitor should be placed close to the receiving end; if the signal is from IC to connector, the coupling capacitor should be placed close to the connector.
2. Choose the smallest package size possible to reduce impedance discontinuity.
3. If the signal working rate of the interface is ≥8Gbps, then the differential DC capacitance of these interfaces is recommended to be optimized as follows:
1) According to the interface, choose to hollow out one or two ground planes. If you hollow out the L2 ground reference layer directly below the capacitor pad, you need to use a separate layer for reference, that is, the L3 layer should be the ground reference layer;
2) If the L2 and L3 ground reference layers are hollowed out, then the L4 layer must be the ground reference layer. The hollow size needs to be determined by simulation according to the actual stack; the reference size based on the EVB first-order HDI stack is given below.
【Note】D1: Center distance between differential coupling capacitors; L: Hollow length; H: Hollow width.
4. Drill 4 ground vias around the coupling capacitor to connect the ground reference layers of the L2~L4 layers, as shown in the figure below.
05
ESD Optimization Recommendations
1. The parasitic capacitance of the ESD protection device must be low enough to allow high-speed signal transmission without degradation.
2. ESD should be placed before the protected IC, but as close as possible to the connector/contact PCB side; before any resistor in series with the signal line; before filtering or regulating devices including fuses.
3. If the signal working rate of the interface is ≥ 8Gbps, then the differential pair ESD devices of these interfaces are recommended to be optimized in the following way. Hollow out the L2 and L3 ground reference layers directly below the ESD pad, and the L4 layer is used as the interlayer reference layer, which needs to be a ground plane. The hollow size needs to be determined through simulation based on the actual stacking in combination with the ESD model.
The reference dimensions of the ESD model ESD73034D based on the EVB-based first-order HDI stack are given below:
4. At the same time, drill 4 ground via holes around each ESD to connect the ground reference layers of the L2~L4 layers, as shown in the figure below.
06
Linker Optimization Recommendations
1. The wiring in the connector should be routed from the center. If the high-speed signal does not have a PIN adjacent to GND at one end of the connector, a GND hole should be added next to it during design.
2. If the signal working rate of the interface is ≥8Gbps, then the connectors of these interfaces must meet the corresponding standard requirements (such as HDMI2.1/DP1.4/PCI-E3.0 protocol standards). Connectors from these manufacturers are recommended: Molex, Amphenol, HRS, etc.
3. Choose to hollow out one or two ground planes according to the interface. If you hollow out the L2 ground reference layer directly below the connector pad, you need to use a separate layer for reference, that is, the L3 layer should be used as the ground reference layer; if you hollow out L2 and L3 The ground reference layer, then the L4 layer needs to be the ground plane, as the reference layer of the interlayer. The hollow size needs to be combined with the connector model and determined through simulation based on the actual stack.
4. It is recommended to drill two ground through holes on each ground pad of the connector, and the ground holes should be as close as possible to the pad.
The reference dimensions for hollowing out based on the EVB first-order HDI stack are given below:
Connector recommended wiring method:
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