PCB design rules 20

1,3W rules

In order to reduce crosstalk between lines, line spacing should be large enough to ensure that, when the center line distance is not less than 3 times the line width can be maintained at 70% of the electric field do not interfere with each other, called 3W rule , 10W using the pitch can be achieved 98% of the electric field do not interfere with each other.

2,20H rules

Since the electric field between the power and ground planes are changed in the outward edge of the plate radiate electromagnetic interference, referred to as the edge effect.

The solution is within the reduced power level, only the electric field in the range of the ground conductive layer. In a H (dielectric thickness between the power and ground) as a unit, if it can be retracted 20H 70% of the field limiting edge in the ground layer; 100H can be retracted to the inner 98% of the field limiting.

3, five - five rules

Selection rule PCB layers, i.e., the clock frequency of 5MHz or the pulse rise time of less than 5ns, the multilayer PCB board shall be used, which is the general rule, and sometimes due to cost considerations, the use of double panels when the structure, in this case, the best side as a complete PCB ground plane layer.

4, ground loop rule

• Loop minimum rules, i.e., the area of ​​the signal line loop circuit comprising therewith as small as possible, the loop area smaller, fewer external radiation, receive external interference is also smaller;
• When split ground plane, taking into account the distribution of the ground plane is important to signal traces, avoids problems due to the slotted ground plane and the like;
• In the double plate design, in a case where the power supply is sufficient space left, the remaining portion should be filled with a reference, and increase the necessary holes, effective to connect the duplex signal, on the possible key signals using ground isolation;
• Some higher frequencies design, special consideration needs to signal its ground plane loop problems, recommends the use of multilayer appropriate.
  

5, crosstalk control

Crosstalk (Cross Talk) refers to the PCB due to the mutual interference between different networks longer parallel wiring caused mainly due to the distributed capacitance and inductance between the parallel lines, the major measures to overcome crosstalk is:

• Increase the pitch of parallel wires, 3W following the rules;
• Into a grounded line of separation between the parallel lines;
• Reducing the distance of the wiring layer and the ground plane;
  

6, shielding

Rule corresponding to circuit ground, and indeed in order to minimize the area of ​​the loop signal is more common in some of the more important signal, such as a clock signal, a synchronization signal; some particularly important, particularly high frequency signals, should be considered copper cable shielding structure design, line isolation is about to land around the cloth line, but also consider how to effectively combine well with the actual ground plane to shield effectively.

7, the alignment direction control

I.e. alignment direction of adjacent layers orthogonal structure, different signal lines to avoid crosstalk between adjacent layers go into the same direction, in order to reduce unnecessary interlayer; (non-parallel to adjacent signal layers, without actually necessarily have orthogonal, subject to alignment space)

Considering the limited space, especially when the higher rate signal, is inserted into the ground plane of each spacer layer wiring, land-line isolation signal to each signal line.

8, a ring-opening alignment checking rules

Look at pictures, we know everything, do not allow floating excess traces appear, in order to avoid "antenna effect", reduce unnecessary interference radiation.

9, impedance matching inspection rules

Wiring width should be consistent with the same network, the line width changes will cause uneven line characteristic impedance, when high transmission speeds will produce reflection, in the design should try to avoid this situation.

Under certain conditions, such as lead connector, when the lead structure similar to the BGA package, and may change the line width can not be avoided, should minimize the effective length of the intermediate portion of the inconsistency.

10, the trace matching rules

In high-speed digital circuits, 1/4 when the delay time is greater than the PCB routing signal rise time (or fall time), i.e., the wiring can be regarded as a transmission line, to ensure that the input impedance and the output impedance of the transmission line signal is a correct match, matching method can take many forms, and matching the selected method and the wiring topology of the network connection concerned.

11, the trace loop checking rules

Prevent the signal line from the loop formed between different layers, prone to such problems in multilayer design, since the ring will cause radiation interference.

12, trace branch length control rule

Try to control the length of the branches, the general requirement is Tdelay <= Trise / 20.

13, the trace resonant rules

It designs mainly for high-frequency signal, i.e., the wiring length can not be an integer multiple of the wavelength relationship therewith to avoid the resonance phenomenon.

14, trace length control rules

That short rule, traces short, in particular the important signal lines such as a clock line.

15, chamfering rule

Traces to avoid right angles and sharp corners.

16, rules decoupling device

Add the necessary decoupling capacitors, the power supply through the first filter capacitor to the device before use, to comply with the decoupling capacitors close principle .

17, device layout partitioning / hierarchical rules

1, the device of different frequencies, typically on the high-speed interface, on the ground plane, both considered divided, and is connected at a single point interface.
2, the hybrid circuit, some digital and analog were placed on both sides of the PCB, the intermediate isolation formation.

18, the control rule isolated copper areas

19, power and ground rule integrity layer

For vias dense region, to avoid holes in the interconnected power and ground hollowed area is formed on the division plane layer, thereby destroying the integrity of the plane of the layer, thus resulting in an increase in the circuit area of ​​the signal line formation .

20, power and ground layers overlap rules

Different power supply layer to avoid overlap in space. Primarily to reduce interference between different power supply, especially in some large voltage difference between the power supply plane overlap must be avoided, it may be considered difficult to avoid the formation interval.

Summarized on this blog in the network, if infringement, please inform, will be deleted.
Reference follows:
PCB routing rules Encyclopedia
the rules (rule 20 large) should be designed to follow a PCB
printed circuit board (PCB) design specifications file VER 1.0