overview
"Noise Problem"
These are four words every board designer will hear. In order to solve the noise problem, it often takes hours to conduct laboratory tests. In order to find out the culprit, but in the end, it was found that the noise was caused by the improper layout of the switching power supply. Solving such problems may require designing new layouts, causing product delays and increased development costs.
overall architecture process
This article will provide guidelines for printed circuit board (PCB) layout to help designers avoid such noise problems. As an example of a switching regulator layout using the ADP1850 dual-channel synchronous switching controller, the first step is to determine the current path for the regulator. The current path then determines the device's location in this low-noise layout design.
Explanation of technical terms
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technical details
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Step 1: Determine the Current Path
In a switching converter design, the high current path and the low current path are very close to each other. Alternating current (AC) paths carry spikes and noise, high direct current (DC) paths can generate considerable voltage drops, and low current paths tend to be sensitive to noise. The key to proper PCB layout and routing is to determine the critical path. Then arrange the device. And provide enough copper area so that high current does not destroy low current. Signs of poor performance are ground bounce and noise injected into the IC and the rest of the system.
The figure shows a synchronous buck regulator design, which includes a switching controller and the following external power devices: high-side switch. Low-side switch. inductance. Input capacitance. output capacitor and bypass capacitor. The arrows in Figure 1 indicate the direction of high switching current flow. These power components must be placed with care. Avoid bad parasitic capacitance and inductance, resulting in excessive noise. overshoot, ringing, and ground bounce.
Switch current paths such as DH.DL, BST, and SW need to be routed away from the controller to avoid excessive parasitic inductance. These lines carry high ol/ot AC switching pulse currents that can reach more than 3A and last for several nanoseconds. High current loops must be small. To minimize output ringing and avoid picking up extra noise. low value. low amplitude signal path. Such as compensation and feedback devices, etc., are very sensitive to noise. These paths should be kept away from switching nodes and power devices to avoid injecting unwanted noise.
The second step layout physical planning
PCB physical planning (floor plan) is very important, and the current loop area must be minimized. And arrange power devices reasonably. Make the current flow smoothly. Avoid sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, thereby eliminating ground bounce.
Figure 2 shows the PCB layout of a dual output buck converter using the ADP1850 switching controller. Note that the layout of the power components minimizes the current loop area and parasitic inductance. Dashed lines indicate high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. In asynchronous controller designs, Schottky diodes replace low-side switches.
The third step mosfet and capacitor
The current waveform at the top and bottom power switches is a pulse with a very high 6l/ot. therefore. The path connecting each switch should be as short as possible to minimize the noise picked up by the controller and the noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate the two FETs in opposite directions so that the switch node is on one side of the pair. And bypass the high-side leakage current to the low-side source with suitable ceramic bypass capacitors. It is important to place the bypass capacitor as close as possible to the MOSFET (see Figure 2) to minimize the inductance around the loop through the FET and capacitor.
The placement of the input bypass capacitor and the input bulk capacitor is critical to control ground bounce. The negative terminal of the output filter capacitor should be connected as close as possible to the source of the low-side MOSFET, which helps reduce loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors, and the recommended value range for these capacitors is 1uF to 22 uF. For high current applications. An additional filter capacitor with a larger value should be connected in parallel, as shown by CIN in the figure.
The fourth step current detection path
To avoid degraded accuracy caused by interfering noise, the current-sense path layout of the current-mode switching regulator must be properly laid out. Dual-channel applications in particular should pay more attention to eliminate any channel-to-channel crosstalk.
The ADP1850 dual buck controller uses the low-side MOSFET's on-resistance, RDS(ON), as part of the control-loop architecture. This architecture senses the current flowing through the low-side MOSFET between the SWx and PGNDx pins. Ground current noise in one channel can couple into adjacent channels. Therefore, it is important to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFETs. In order to accurately detect the current. Connections to SWx and PGNDx nodes must use Kelvin detection techniques.
Part 5, Gate Driver Path
The pole drive traces (DH and DL) also deal with high ol/ot, which tends to produce ringing and overshoot. These traces should be as short as possible. It is best to wire directly. Avoid using feedthroughs. If vias must be used, use two vias per trace to reduce peak current density and parasitic inductance.
A small resistor (about 20 to 40 Ω) in series with the DH or DL pin can slow down the gate drive, which also reduces gate noise and overshoot. Alternatively, a resistor can also be connected between the BST and SW pins (see Figure 6). Reserving space with 00 gate resistors during layout increases flexibility for later evaluation. The increased gate resistance prolongs the gate charge rise and fall times, resulting in higher switching power losses in the MOSFET.
summary
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Know the current path. Its sensitivity and proper device placement. It is the key to eliminating noise problems in PCB layout design. All Analog Devices power device evaluation boards use the above layout guidelines for optimum performance. Evaluation board documents UG-204 and UG-205 detail the layout of the ADP1850. Note that all switching power supplies have the same components and similar current path sensitivities. therefore. The guidelines illustrated with the ADP1850 as an example for a current-mode buck regulator also apply to the layout of a voltage-mode and/or boost switching regulator.