PCB Modular Design 13 - FLASH, DDR and eMMC High Speed PCB Layout and Routing Design Specifications

PCB modular design 13 - FLASH and DDR high-speed PCB layout design specification

Link: ROM, RAM, FLASH, DDR, EMMC Encyclopedia

1. Flash high-speed PCB layout design specification

1. Introduction to Flash

At present, there are mainly two types of Flash, NOR Flash and NADN Flash.
The reading of NOR Flash is the same as that of our common SDRAM. Users can directly run the code loaded in NOR FLASH, which can reduce the capacity of SRAM and save costs.
NAND Flash does not adopt the random read technology of the memory. It reads one block at a time, usually 512 bytes at a time. Flash using this technology is relatively cheap.
Generally, small-capacity NOR Flash is used because of its fast reading speed, and it is mostly used to store important information such as the operating system,
while large-capacity NOR Flash is used. The most common NAND FLASH application is DOC (Disk On Chip) used in embedded systems. And the "flash drive" we usually use can be erased online.

FLASH: It is a kind of non-volatile memory. The physical characteristics of flash memory are fundamentally different from common memory:
at present, all kinds of DDR, SDRAM or RDRAM are volatile memories, and the data in the memory cannot be kept as long as the current supply is stopped. , so every time the computer is turned on, the data needs to be reloaded into the memory; flash memory can keep data for a long time without current supply, and its storage characteristics are equivalent to hard disks. The base of the device's storage medium.
NOR FLASH: Its characteristic is that it can be executed in the chip, and the application program can be run directly in the flash memory without having to read the code into the system RAM.
The small capacity under 1~16M has high cost-effectiveness, but the very low writing and erasing speed greatly affects its performance.
His reading is the same as our common SDRAM reading.
NAND FLASH: Nand-flash memory has the advantages of large capacity and fast rewriting speed. It is suitable for the storage of large amounts of data, such as embedded products including digital cameras, MP3 walkman memory cards, and small U disks.
Reading is performed one block at a time, usually 512 bytes at a time.
Users cannot directly run the code on NAND Flash, so many use NAND Flash and make a small NOR Flash to run the startup code.

2. NOR and NAND performance comparison

FLASH flash memory is a non-volatile memory that can be erased, written and reprogrammed in blocks of memory cells called blocks. The write operation of any flash device can only be performed in empty or erased cells, so in most cases, the erase must be performed before the write operation. It is very simple for NAND devices to perform erase operations, while NOR requires that all bits in the target block be written to 1 before erasing.

Since erasing NOR devices is performed in blocks of 64-128KB, the time to perform a write/erase operation is 5s. On the contrary, erasing NAND devices is performed in blocks of 8-32KB. The operation takes only 4ms at most.

The difference in block size when performing erase further widens the performance gap between NOR and NADN, and statistics show that for a given set of write operations (especially when updating small files), more erase operations must be performed in carried out in NOR-based units. Thus, when selecting a storage solution, designers must weigh the following factors:

● The reading speed of NOR is slightly faster than that of NAND.

● The writing speed of NAND is much faster than that of NOR.

● NAND's 4ms erasing speed is much faster than NOR's 5s.

● Most write operations require an erase operation first.

● The erasing unit of NAND is smaller, and the corresponding erasing circuit is less.

(Note: The erasing time of NOR FLASH SECTOR varies depending on the brand and size. For example, for 4M FLASH, some SECTOR erasing time is 60ms, while some require a maximum of 6s.)

3. The use of NAND Flash

HDD refers to mechanical hard disk, which is a traditional ordinary hard disk, including: platter, magnetic head, disk rotating shaft and control motor, magnetic head controller, data adapter, interface, and cache.

SDD (Solid State Drives) is a solid state drive, including: control unit, storage unit (DRAM chip/FLASH chip).

Difference: HDD searches for data mechanically, so the shock resistance is much lower than that of SSD, and the data search time is also much lower than that of SSD.

4. FLASH pin definition

According to the above picture, the translation is as follows:

1. I/O0 ~ I/O7: Used to input address/data/command and output data.

2. CLE: Command Latch Enable, command latch enable, before inputting the command, first set CLE enable in the mode register

3. ALE: Address Latch Enable, address latch enable, before inputting the address, first set ALE enable in the mode register

4. CE#: Chip Enable, the chip is enabled, before operating Nand Flash, you must first select this chip to operate

5. RE#: Read Enable, read enable, CE# must be enabled before reading data.

6. WE#: Write Enable, write enable, before writing and fetching data, WE# must be enabled first.

7. WP#: Write Protect, write protection

8. R/B#: Ready/Busy Output, ready/busy, mainly used to detect whether these operations are completed after the programming/erasing command is sent, busy, indicating that the programming/erasing operation is still in progress, and ready indicates that the operation is completed.

9. Vcc: Power, power supply

10. Vss: Ground, ground

11. NC: Non-Connection, undefined, not connected.

5. Timing diagram of Nand Flash data read operation

6. FLASH reference schematic diagram

7. PCB layout design guidelines

1) Layout:

(1) NAND should be placed close to the main control;

(2) Decoupling capacitors are placed close to NAND;

(3) RE, WE, and DQS signal series resistors are placed close to the main control, and the distance between the series resistance and the main control connection is ≤300mil;

2) Signal line routing requirements:

(1) The wiring between NAND and the main control wiring is ≤2000mil;

(2) The trace impedance is 50 ohms;

(3) Line spacing ≥ 2 times the line width;

(4) D0~D7, RE, WE are equal in length to DQS, control ≤300mil;

(5) The number of vias used on D0~D7 should be the same as possible;

(6) Be sure to ensure that the trace reference plane is complete;

(7) Try to avoid high-frequency signals in the wiring;

(8) The line width of VCC/VCCQ is not less than 12mil, or directly use copper plating instead of power supply wiring; if there are vias on the power supply line, the number of vias should be no less than 2, so as to avoid the impact of current limiting via vias on power supply;

FLASH actual combat case display

2. DDR high-speed PCB layout design specification

1. What is DDR?

DDR=Double Data Rate double rate, DDR SDRAM=double rate synchronous dynamic random access memory, people are used to call it DDR, among them, SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, that is, synchronous dynamic random access memory. DDR SDRAM is the abbreviation of Double Data Rate SDRAM, which means double-rate synchronous dynamic random access memory. DDR memory is developed on the basis of SDRAM memory and still uses the SDRAM production system. Therefore, for memory manufacturers, it is only necessary to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce cost.
Some working conditions of DDR:

It can still be seen that with the upgrading of DDR, the bus clock frequency is getting higher and higher, and the transmission rate is getting faster and faster, and the working voltage is getting lower and lower, gradually moving towards low power consumption, high The direction of speed development also brings higher requirements for impedance matching for DDR wiring layout.

2. DDR pin definition

The following figure is the general definition of DDR pins. DDR pins can be divided into 3 categories. The first category is the power line, VDDQ, VSSQ, VDD, VSS, VREF are all power lines; the second category is the data line
. High and low 8-bit data lines are a group, composed of D0-D7+LDM+ data differential pairs and D8-D15+UDM+ data differential pairs, generally 11 lines are a group of data lines; the third type is address lines, except for data lines and power
supply line, and the rest are uniformly divided into address lines, with a pair of clock differentials.

3. DDR PCB layout rules

The layout can be carried out according to the number of DDRs:

1. One piece of DDR

When a piece of DDR is used, the layout is point-to-point, leaving a certain space for wiring

2. Two pieces of DDR

When two pieces of DDR are used, it is symmetrical to the center position of the corresponding DDR pin of the CPU, leaving a certain space for winding, and paying attention to the positions of series resistors and parallel resistors

When there is exclusion in the middle, the distance between DDR and the center: 800~1000mil
When there is no exclusion in the middle, the distance between DDR and the center: 600~800mil.
It is necessary to plan the layout structure reasonably. According to the preface, two pieces of DDR need at least Three wiring layers, assuming a 6-layer board and three wiring layers, take the T-point structure as an example: it

can be seen from the figure that because it is a BGA package, it is difficult to route the surface layer directly, and at the same time the high eight-bit data Intersect with the lower eight-bit data in pairs. Theoretically, the data line can be completed in one layer after laying out the layout. Lines, one routing layer for each of the eight high and low bits. At the same time, it should also be noted that the center structure of the T point generally uses the inner layer, so try not to let the inner layer data line and the inner layer address line have any gaps when routing inside the DDR. The conflict is as follows:

the left is the data line, use the bottom blue to go, the right is the T point, use the inner tan to go, if you use tan to go, theoretically it is no problem at all
, but try to stagger the peak Travel, avoid too little space for wiring! ! !

Let me add how T goes out. Basically, if there are two DDRs, you must first go to the T point inside the DDR, and then go to the outside T point. The best distribution is that the points on both sides are staggered and placed. Two factions, and generally speaking, the address lines on both sides are uneven. The two rows of vias in T should be distributed evenly as much as possible. The distance between vias and vias in point T is generally the DDR you fanned out. The spacing between the pad vias, otherwise it will not be very good. Remember to add this point. The spacing is best to be consistent with the vias of the DDR.

Then there is the T-point wiring. Basically, it is impossible for you to meet the 3W principle at the T point, just like your BGA cannot meet the 3W principle. If you can meet it, you are awesome. I admire you. Hee hee hee, the T point is very difficult. Basically, you know how to go to the T point, but when fanning holes, allocating holes is also a science, which you have to understand in practice.

Then the CPU wiring is led to the T point of the DDR. In fact, there is nothing special about it. Try to get out of the surface layer. If you can’t get out, go to the bottom layer. If you can’t get out, go to the bottom layer. Use the third layer to switch the position and route the wires, leaving enough space for the same length. (In theory, the four wiring layers are the most comfortable, based on cost considerations)

3. Four pieces of DDR and above

For four-chip DDR or eight-chip DDR, the two tops and bottoms are generally attached together, which is the same as two-chip DDR. There is nothing new to say, the meaning is in place, right?

4. PCB routing principle of DDR

Wiring requirements (recommended to refer to Layout Guide or simulation results)

Characteristic impedance: single-ended 50 ohms, differential 100 ohms

Try to run every 10 data lines on the same layer (DO-D7, LDM, LDQS), (D8-D15.UDM, UDQS)

The distance between the signal lines meets the 3W principle, and the distance between the data lines, address (control) lines, and clock lines is kept at least 20mi or at least 3W

If space permits, a ground wire should be added between them for isolation. The recommended width of the ground wire is 15-30mil

The VREF power trace first passes through the capacitor and then enters the pin. The recommended width of the Vre power trace is not less than 20mil, and the distance between it and other signal lines on the same layer is preferably 20mil.

All signal lines must not be cross-split and have a complete reference plane. When changing layers, if the reference layer is changed, attention should be paid to adding return vias or decoupling capacitors

For more than two DDR wiring topology, the remote branch is preferred, and the via hole at point T is drilled in the middle of the two DDR

The daisy chain needs to be verified by simulation or required by the chip Layout Guide. (Generally, only those masters that support read-write balance can support the daisy chain)

All DDR signals are at least 30-40mil away from the corresponding reference plane edge. Any signal that is not part of the DDR must not be referenced to the DDR power supply

equal length rule

The length of the data line is equal to the reference of DQS, and the length of the address line, control line, and clock line is equal to the reference of the clock line. If there is no reference to the clock line in the software, it must be manually selected as the reference line.

The maximum length of the data line should not exceed 2500mil, the error range of the length within the group should be controlled at +/- 25ml, the length error of DQS and clock lines should be controlled at +/-250mil, and the maximum error of single-chip DDR should not exceed 1000mil:

The error range of the address line is controlled within +/-100mil:DQS, and the error range of the clock differential pair is controlled within +/-5mil. When designing the impedance, the inner pair spacing should not exceed 2 times the line width. The actual length of the signal should include the length of the component pins, try to obtain the length of the component pins, and import it into the software.

Summary
If you route directly without considering a general plan, it is a waste of time.

5. When designing and wiring DDR PCB, the choice of topology structure

In PCB design, when we deal with the DDR part, we will choose a topology. Generally, DDR has two topologies: T-point and Fly-by. So what are the application scenarios and differences between these two topologies?

T-point topology: the signal line from the CPU passes through a via hole and then connects to both sides. The bifurcation point is generally at the center of the signal.

Fly-by topology: Usually, after the signal comes out of the chip, how to pass through the first signal point and then pass through the second signal point to connect in turn until the end

From the point of view of our wiring and equal length: it is generally recommended to adopt the Fly-by topology, and the T point is not easy to deal with when the length is equal, so we try to consider the T point topology when the board space is sufficient. In this way, the length of the signal line will be shorter, which can better ensure the quality of the signal. Generally, we can use T-point and Fly-by when four-chip and four-chip DDR are used. If there are more than four chips, it is recommended to use DDR. Use Fly-by topology, or use T-point DDR top and bottom stickers for a process. The two pieces of DDR on the top and bottom stickers are connected by T points. After the connection, the line is pulled to the symmetrical center of the DDR for T-point connection.

From the perspective of our timing requirements: we need to see if DDR supports read-write balance. If it does not support read-write balance, then we cannot use the Fly-by topology. The advantage of using the T-point structure lies in the timing The signals can arrive at the same time, and when using the Fly-by topology, the DDR that supports read-write balance can make an internal adjustment even if you cannot arrive at the same time.
If we use the Fly-by topology in the DDR that does not support read-write balance, the operation will be less than the rated power, the speed will not meet the requirements, and the frequency may need to be reduced to work normally, so this is also the DDR design. Some problems that are often encountered, a little improper handling will lead to DDR not working properly.

So what points should we pay attention to when we deal with DDR:

1. We need to ensure that our DDR signal has a complete reference plane.

2. The equal length of DDR must meet the requirements in the data sheet, and the error should be made smaller when there is sufficient space.

3. When the length is equal, the 3W principle needs to be met.

4. Signals and power supplies that have nothing to do with DDR cannot cross the DDR area.

5. Try not to wind wires inside the BGA when waiting for a long time.

6. Important signals, such as differential, should be packaged when space permits.

7. For any non-DDR signal, the DDR power supply must not be used as a reference plane.

8. For example, the edge of the reference plane for all DDR signals should maintain a distance of about 40mil

9. After the DDR is finished, make a circle of ground vias in the DDR area.

10. All DDR signals need to be designed in strict accordance with the impedance requirements in the data sheet.

11. The DDR part should be kept away from interference sources during layout.

3. EMMC high-speed PCB layout design specification

1 Introduction

eMMC (Embedded Multi Media Card) is the abbreviation of embedded multimedia card, which is mainly designed for the characteristics of mobile phones and tablet computers.
Its essence is to add a controller on the basis of NAND Flash and reserve a standard interface.

2. General introduction of eMMC signal

The PIN pins of eMMC particles are mainly divided into three groups: power pins, control signal pins, and data signal pins.

power pin

VCCQ voltage: This voltage is determined by the VCCIO of the CPU data bus (the VCCIO value of the eMMC bus must be consistent with VCCQ)

VCC voltage: This voltage is the core voltage;

VDDIM: Internally connected to the core power supply terminal, the main function is to stabilize the core voltage, this PIN pin is directly connected to a 1μF capacitor to ground.

control signal pin

CLK: The clock signal output from the Host for data synchronization.

CMD: Mainly used for Host to send instructions to eMMC and eMMC to send requests to Host.

DS clock: DS clock is sent to Host by eMMC, which is used for data reception synchronization between Host and eMMC. Only in HS400 mode, the DS pin needs to be used.

Note: In HS200 mode, you need to use CLK, CMD, D[3...0]; in HS400 mode, you need to use CLK, CMD, D[7...0], DS.

control signal pin

CLK: The clock signal output from the Host for data synchronization.

CMD: Mainly used for Host to send instructions to eMMC and eMMC to send requests to Host.

DS clock: DS clock is sent to Host by eMMC, which is used for data reception synchronization between Host and eMMC. Only in HS400 mode, the DS pin needs to be used.

3. eMMC package

For the package of eMMC, it can be divided into 153ball and 169ball according to the PIN pins, but the pins of these two types are compatible. It is known that the latter has 16 more empty pins for chip fixing, without any signal definition. The size of the chip package Vanke is determined by:

11.5*13

12*16

14*18

16*20

The real thing is as follows:

Usually, we will reserve the largest size in PCB Layout, and the pad will be drawn as 169ball, which can be compatible with 153ball chips.

4. Hardware circuit design

Power part circuit

Control and Data Pins

other parts

5. Suggestions for PCB layout

The PCB routing layout and filter capacitor placement suggestions for the eMMC5.1 version are as follows:


Recommended decoupling capacitors:

— VCCQ ≥ 0.1 uF x1 and 2.2 uF x1 (this cap should be as close as possible to the C6 ball) and 1 x 1uF

— VCC ≥ 0.1uF x1 and 2.2uF x1

— VDDI ≥ 0.1uF x1 and 2.2uF x1

The schematic reference design is as follows:



PCB layout reference design
Reference design 1

Reference Design 2

Reference Design 3

Reference Design 4

Reference Design 5

The preceding reference design shows an example layout for a v5.x eMMC device using roughly 6mil wide traces and 12mil/24mil vias. One thing to note is that due to the spacing of the eMMC balls, the line width may need to be adjusted so that the lines can pass through the "NC" balls.

From reference design 1 to 4, the thickness adjustment of the cable is used to avoid NC. Reference design 5 adopts the layout method that directly passes through the NC PIN. Regarding reference design 5, the manufacturer’s suggestions are as follows: e·MMC signals can

be fanned out through NC pins. No internal connection is present for NC pins. Micron recommends that e·MMC signals not be fanned out through RFU pins.

e·MMC signals can be fanned out through NC pins. There are no internal connections to the NC pins. Micron recommends against fanning out e·MMC signals through the RFU pins.

You can perform pcb layout on eMMC according to your own knowledge, this article is just for reference. enjoy it