Challenge (a), electronic system design faces
With the large-scale system design complexity and increased integration of electronic systems designers are engaged in more than 100MHZ circuit design, the operating frequency of the bus has reached or exceeded 50MHZ, some even more than 100MHZ. Currently about 50% of the clock frequency than the design of 50MHz, nearly 20% of the design frequency exceeds 120MHz.
When the system operates at 50MHz, it will have transmission line effects and integrity issues signals; and when the system clock reaches 120MHz, high-speed circuit design knowledge unless otherwise conventional method based PCB design will not work. Therefore, high-speed circuit design technology has become a means to design electronic systems designers must be taken. Only through the use of high-speed circuit designers design techniques to achieve the controllability of the design process.
(B) What is the high-speed circuit
If the frequency is generally considered the digital logic circuit reaches or exceeds 45MHZ ~ 50MHZ, and operation of the circuit on the frequency of the entire electronic system has accounted for a certain amount (for example 1/3), called high-speed circuit.
In fact, the frequency of the harmonic signal edge is higher than the frequency of the signal itself, is rapidly changing signal rising and falling edges (or signal transition) results led to unintended signal transmission. Thus, if the wire is generally agreed propagation delay is greater than 1/2 of the rise time of the drive end digital signal, such that the high-speed signal and generates a signal transmission line effects.
Transient delivery signal occurs in a signal state change, such as a rise or fall time. From the driving signal to the receiver after a fixed period of time, if the transmission time is less than 1/2 of the rise or fall time, the reflected signal from the receiving end before reaching the drive end signal changes state. Conversely, the reflected signal will change states after the signal reaches the drive end. If the reflected signal is very strong, there may be superimposed on the waveform of the logic state change.
Determining (C), the high-speed signal
Above we defined the preconditions for transmission line effects occur, but how that line the delay is greater than 1/2 of the drive end signal rise time? Generally, a typical value of the signal rise time may be given by the manual device, and the signal propagation time is determined by the actual wiring length in the PCB design. Wiring length (delay) of the lower picture shows the signal rise time and allows correspondence.
Per inch of the PCB delay is 0.167ns .. However, if multiple vias, a multi-pin devices, multi-set constraints on the wire, the delay will increase. Signal is typically a high-speed logic device rise time of about 0.2ns. If the board has a chip GaAs, the maximum wiring length of 7.62mm.
Rise time Tr of the signal provided, Tpd propagation delay of the signal line. If Tr≥4Tpd, signal falls safe area. If 2Tpd≥Tr≥4Tpd, signal falls uncertain area. If Tr≤2Tpd, signal falls problem areas. For signal falls uncertainty area and problem areas, high-speed routing method should be used.
(D) What is the transmission line
PCB板上的走线可等效为下图所示的串联和并联的电容、电阻和电感结构。串联电阻的典型值0.25-0.55 ohms/foot，因为绝缘层的缘故，并联电阻阻值通常很高。将寄生电阻、电容和电感加到实际的PCB连线中之后，连线上的最终阻抗称为特征阻抗Zo。线径越宽，距电源/地越近，或隔离层的介电常数越高，特征阻抗就越小。如果传输线和接收端的阻抗不匹配，那么输出的电流信号和信号最终的稳定状态将不同，这就引起信号在接收端产生反射，这个反射信号将传回信号发射端并再次反射回来。随着能量的减弱反射信号的幅度将减小，直到信号的电压和电流达到稳定。这种效应被称为振荡，信号的振荡在信号的上升沿和下降沿经常可以看到。(E), transmission line effects
Transmission line model based on the above definition, sum up, the entire transmission line circuit design will bring less effect.
· Signals reflected signal Reflected
-delay timing errors and the Timing errors & Delay
· across multiple logical level threshold error Switching False
· overshoot and undershoot Overshoot / Undershoot
· Crosstalk Noise Induced (or crosstalk)
· EMI radiation electromagnetic radiation
5.1 reflection signal
if a trace is not properly terminated (termination), then the pulse signal from the drive side is reflected at the receiving end, a desired effect without causing the distortion of the signal profile. When significant distortion deformation can cause a variety of errors caused by design failures. At the same time, signal distortion deformation sensitivity to noise increases, can cause design failures. If this is not enough to consider, EMI will increase significantly, which would not only affect the results of its own design, will result in failure of the entire system.
Mainly reflected signals generated: long traces; not match the end of the transmission line, and excess capacitance or inductance impedance mismatch.
5.2 delay and timing error
signal delay and timing errors as follows: Signal period of time does not signal transitions when the change between high and low logic level thresholds. Excessive signal delay may lead to confusion timing errors and device functionality.
The problem usually occurs when there are multiple receiving end. Circuit designer must determine worst case time delay to ensure the correctness of the design. Cause signal delay produced by: drive overload, a long circuit.
5.3 across multiple logic level threshold error
signal during transitions may span multiple logic level thresholds leading to this type of error. Across multiple error threshold logic level is a special form of the oscillation signal, i.e., the oscillation signal of the logic level occurs in the vicinity of the threshold, the logic level across multiple threshold logical cause dysfunction. Reason why a reflection signal produced: long traces, not the end of the transmission line, and excess capacitance or inductance impedance mismatch.
5.4 overshoot and undershoot
reason to go from the red line is too long or the signal changes too fast both rushed over and under. Although most elements of the receiving end input protection diode protection, but sometimes overshoot element levels far exceed the supply voltage range, damage to the components.
5.5 Crosstalk
Crosstalk performance in a signal line when the signal through the PCB adjacent to the signal lines will induce a signal related to, we call crosstalk.
The closer the ground signal line, the larger the line spacing, the smaller the crosstalk signal generated. Asynchronous signals and clock signals are more prone to crosstalk. Therefore methods for solving the crosstalk signal is removed or the mask signal crosstalk is serious interference.
5.6 electromagnetic radiation
EMI (Electro-Magnetic Interference) an electromagnetic interference problems caused by excessive electromagnetic radiation and comprising both sensitive to electromagnetic radiation. EMI performance when running digital system power-up, the surroundings will radiate electromagnetic waves, which interfere with the normal operation of electronic equipment in the surrounding environment. The main reason is that it produces high frequency circuit and the layout is unreasonable. At present, the software tool simulation conducted EMI, but EMI simulators are expensive, simulation parameters and boundary conditions very difficult, which will directly affect the accuracy and usefulness of simulation results. The most common practice is to control the various EMI design rules used in every aspect of the design rules for implementing various aspects of the design of drive and control.
(Vi), the method to avoid transmission line effects
influence the transmission line for the above problems introduced methods to control these effects we talk about the following aspects.
6.1 strict control of critical cable length trace
if there is an edge high-speed hopping design must take into account transmission line effects problems present in the PCB. Now a high clock frequency commonly used in fast integrated circuit chip is such a problem. To solve this problem there are some basic principles: If a CMOS or TTL circuit design, the operating frequency is less than 10MHz, the wiring length should be less than 7 inches. 50MHz operating frequency wiring length should not exceed 1.5 inches. If the operating frequency reaches or exceeds 75MHz wiring length should be one inch. For GaAs chip maximum wiring length of 0.3 inches. If you exceed this standard, the problem of the transmission line.
6.2 rational planning wiring topology
Another solution to transmission line effects is to choose the correct routing path and terminal topologies. Topology means wiring traces and the wiring structure of a sequential network cable. When a high-speed logic devices, unless traces kept short branch lengths, or the edge of a rapidly changing signal will be away trunk branch signal line traces distorted. Under normal circumstances, PCB traces two basic topologies, namely a daisy chain (Daisy Chain) and star wiring (Star) distribution.
For daisy chain wiring, the wiring from the drive end begins, and sequentially arrive at each receiving end. If a series resistor to alter the signal characteristics, the series resistance should be located close to the driving end. Control traces harmonic interference aspect, the daisy-chain the best alignment. But this cabling mode lowest pass rate, 100% cloth is not easy to pass. In actual design, we make the daisy-chain branch wiring length as short as possible, the length of the security value should be:. Stub Delay <= Trt * 0.1
For example, a high-speed TTL circuit branch end length of less than 1.5 inches. This topology wiring space is small and can be occupied by a single resistor matching termination. However, this alignment structure is not synchronized such that at the receiving end receives a different signal in the signal.
Star topology can effectively avoid synchronization clock signal, but the completion of a high density wiring board PCB hand difficult. Automatic routing is the best way to accomplish the star wiring. Each branch termination resistors are required. The resistance of the terminating resistor and should match the characteristic impedance of the wiring. This can be done by hand calculations may be calculated and the characteristic impedance termination resistor value values CAD tools.
Using a simple two terminal resistors in the above example, the actual selectable more complex matched termination. The first option is to match the RC terminal. RC matching terminal can reduce power consumption, but can only be used to work a relatively stable signal. This method is best to match the clock line signal processing. The disadvantage is that the terminal RC matching capacitance may affect the shape and the propagation speed of the signal.
Series resistor matched termination no additional power consumption, but it will slow down the transmission signal. In this way the time delay for the bus driver circuit little effect. Matching the series resistance is advantageous in that the terminal can be used to reduce the number of connections and the density of devices on a board.
Finally, a way for separating the terminal match, the matching element in this way needs to be placed near the receiver. The advantage is not pulled low signal, and may well avoid noise. Typical for the TTL input signal (ACT, HCT, FAST).
Further, for the termination type and mounting type package resistance must also be considered. SMD surface resistance typically has a lower inductance than a through hole element, the SMD package component choice. If the selected normal line resistance, there are two installation options: vertically and horizontally.
Mounted in a vertical mounting pin resistor is short, it can reduce the thermal resistance between the resistor and the circuit board, the heat resistance more easily into the atmosphere. But the longer the vertical mounting of the inductor resistance increases. A lower horizontal installation because the installation has a lower inductance. But overheated resistor will drift, in the worst case resistance becomes open, causing the end of PCB traces match fails, a potential failure factors.
6.3 A method of suppressing electromagnetic interference
good signal integrity to improve the electromagnetic compatibility of the PCB (EMC). Wherein the PCB is very important to ensure good grounding plate. It designed using a complex signal with a ground plane layer is a very effective method. In addition, the density of the outermost layer of the circuit board minimum signal also a good way to reduce electromagnetic radiation, this method can be "surface area of the layer" "Build-up" designed to do PCB implemented. Increasing the surface area of the layer is achieved by a thin insulating layer and a microporous layer through the normal process of PCB in combination, resistors and capacitors may be buried in the subsurface, wiring density per unit area will be nearly doubled, thus reducing the volume of the PCB. PCB has reduced the area of the topology of traces huge impact, which means a reduced current loop, the reduced branch trace lengths, and the electromagnetic radiation is approximately proportional to the area of the current loop; feature means that while a small volume of high-density lead pin package device can be used, which in turn causes decrease wire length, thereby reducing the current loop, to improve the electromagnetic compatibility characteristics.
6.4 Other techniques may be employed
to reduce the voltage on the integrated circuit chip power transient overshoot, decoupling capacitors should be added as an integrated circuit chip. This burr can effectively remove the influence on the power supply and to reduce the radiation power in the loop on the printed board.
When the decoupling capacitor is connected directly to the power supply of the integrated circuit rather than leg tube is connected to the power supply layer, its smooth burr best. That's why there are some devices with the socket decoupling capacitors, and some devices require decoupling capacitors distance from the device to be small enough.
Any high speed and high power devices should be placed together to reduce the supply voltage transient overshoot.
If there is no power supply layer, the length of the loop formed in power connection between the circuit and the signal, the radiation source becomes easy sensing circuit.
Traces constituting a case does not pass through the same network cable or other traces of the loop or open loop. If the loop through the same network line other traces are closed loop. In both cases, the effect of forming the antenna (linear antenna and a loop antenna). External antenna generates EMI radiation, but also sensitive to its own circuit. Loop is a problem that must be considered, because it is approximately proportional to the area of the radiation generated by the closed loop.
Conclusion
high speed circuit design is a very complex design, ZUKEN's high-speed algorithm wiring (Route Editor) and EMC / EMI analysis software (INCASES, Hot-Stage) applied to the analysis and discovery problems. The method described in this paper is designed for high-speed circuit design to solve these problems. In addition, there are a number of factors need to be considered when performing high-speed circuit design, these factors sometimes opposing each other. The layout position near the high-speed device, although the delay may be reduced, but may produce significant crosstalk and thermal effects. Therefore, the design, the need to weigh the factors, to make a comprehensive trade-offs; both meet the design requirements, and reduce design complexity. High-speed PCB design tools controllability constitute the design process, only controlled, is reliable, but also to be more about proofing pcb circuit board design www.jiepei.com/g532