(5) Printed circuit board or PCB layout
After all circuit design is completed, the next step is circuit board layout. This is a very critical step in the development process because the effectiveness of the filter circuit depends on the placement of the components relative to the DSP pins. Additionally, board layout has a large impact on noise, crosstalk, and transmission line effects, so optimizing the layout can minimize these effects. First, the designer needs to determine the minimum number of layers for the PCB and then configure the board stackup. Here are some general guidelines.
Experiment with the layout and refer to the DSP reference design package to find the minimum number of layers required to output the signal from the DSP. If possible, copy the exact layout recommended by TI. Consider the need to shield high-speed signals between ground and power planes. Do buses such as USB, DDR, Ethernet, and RapidIO require strict differential impedance specifications? Does PCB manufacturing require a certain trace width and spacing? This determines whether traces can be routed between the balls of a small-pitch BGA package. For good signal integrity and minimal skin effect losses, trace widths should be kept between 4 mils and 12 mils. A common choice is 5 mil trace and 5 mil spacing.
Is one power plane and one ground plane sufficient?
Do DSP systems require controlled impedance boards? This approach is more expensive but can optimize the circuit from a signal integrity perspective plate.
Two PCB stackup topologies are commonly used: adjacent power planes and non-adjacent power and ground planes. Figure 5-1 shows what each layer can and cannot do when implementing a design on a 6-layer PCB for adjacent power and ground topologies.
When using this stacked structure, you need to pay attention to the following points:
As shown in the Cpp formula, the distance d between the power and ground planes determines the board capacitance. Shortening the distance increases capacitance and also reduces high frequency impedance. The limiting factor is how tight the layers can be while maintaining design quality and reliability.
Route high-speed signals on layers next to power and ground planes.
The best routing layer is layer 2 because it is close to the ground plane. This provides an optimal current return path, helping to reduce radiation. This is why an adjacent power and ground topology is recommended for DSP systems operating at extremely high frequencies.
The adjacent power and ground topology is not suitable for DSP systems because DSP systems require many layers to route signals away from the DSP and interface with other circuits.
Figure 5-2 shows a typical PCB stackup for a non-adjacent power and ground topology. The power and ground layers are located on layer 5 and layer 2 respectively. Layer 3 is best for high-speed trace routing, while Layers 1, 4, and 6 are also acceptable. As shown in the figure, each routing layer is close to a ground plane or a power plane. Layer 3 is best because not only is it close to the ground plane, but it is protected by the power plane beneath it. This solution is most suitable for DSP systems that are difficult to wire and whose operating frequency is not very high. One thing to remember is that for systems operating above 300MHz, board capacitance becomes very important.
Here are the rules for designing non-adjacent board stackups:
For non-adjacent topologies, the capacitance equation Cpp shows a lower board capacitance and a higher board impedance between the power and ground planes. This is contrary to the low noise and low EMI requirements of the system.
This topology requires more high frequency capacitance to compensate for board characteristics.
Once the board stackup has been decided, the next step is to determine the best way to route the signals on the routing layers. Table 5-1 shows the advantages and disadvantages of the two major signal routing techniques
Designers often compromise and use two topologies, where some critical signals are routed between ground and power planes.
PCB routing and circuit board stackup are major sources of electromagnetic interference, so designers need to adopt best practices to reduce emissions. One example is using a mirror layer, a ground plane that sits next to a routing layer to provide a low-inductance current return path for high-speed signals. The mirror layer helps reduce the current loop area and minimizes potential differences on the ground plane. Experiments conducted by Clayton compared the EI of PCBs with and without image planes. They demonstrated that PCBs with mirrored planes reduced EMI by approximately 15dB across the spectrum.