[FPGA] AM modulation and demodulation based on vivado (verilog) (1. Theoretical knowledge)

1. Technical indicators

To complete the signal AM modulation and demodulation function, the specific requirements are as follows:
(1) Carrier signal frequency range: 1M-10MHz, resolution 0.01MHz;
(2) Modulation signal is a single-frequency sine wave signal, frequency range: 1kHz-10kHz, resolution Rate 0.01kHz;
(3) Modulation depth 0-1.0, step 0.1, accuracy better than 5%; (
4) Use MATLAB to compare modulation signal and demodulation signal indicators;
(5) Carrier signal frequency, modulation signal frequency and modulation depth It can be set;
(6) Complete the simulation test verification.

2. AM principle

The principle is very simple, you can refer to the relevant bibliography for details.
The modulation principle is this formula:
insert image description here
the demodulation principle is full-wave rectification + low-pass filtering.

3. Scheme design

The principle block diagram is as follows:
insert image description here

first part

The first part is the generation of modulation signal and carrier signal: calculate the bit width according to the resolution, call the DDS IP core twice to generate modulation signal and carrier signal respectively.
The dds core needs to be called to generate the modulation signal and carrier signal. According to the formula
insert image description here
, fclk is the system clock, ▲θ is the frequency control word, B is the bit width of the phase accumulator, and fout is the output signal frequency.
For the carrier signal, when B = 16, the frequency resolution is. insert image description here
For the modulation signal, when B = 24, the frequency resolution is insert image description here
the bit width of the phase accumulator. You can determine it according to the frequency resolution index requirements and actual simulation results. It is not necessary to take these two numbers.

the second part

The second part is the modulation part: first multiply by the modulation depth, then superimpose the DC component, and finally multiply by the carrier, all of which can be realized by calling the multiplier and adder IP core.
Set the output bit width of DDS to 8 bits, then the amplitude of the modulation signal is -128 to 127 (the actual simulation is -126~126), and the DC component needs to be superimposed to make the amplitude of the modulation signal all positive. Assuming that the DC component A is 127, the standard formula can be obtained.
As for the modulation depth, since decimals cannot be displayed directly, we can round up ma*256, multiply it with the modulation signal, and then shift the result to the right by 8 bits.

the third part

The third part is the demodulation part: the envelope detection demodulation method is adopted, that is, full-wave rectification is performed first, all negative values ​​are reversed, and then low-pass filtering is performed, and finally the demodulation signal can be obtained by truncation, which can be obtained by Write a program and call the fir filter core to realize it.
Before that, you need to prepare the filter coefficient file with matlab.
Enter filterDesigner in the command line window and press Enter.
The filter selects fir low-pass filter, the filter order is set to 100 (selected according to the output effect, not necessarily scientific), the sampling frequency is 25MHz (as long as it is >2*10MHz), the cutoff frequency is 25kHz (as long as > 10kHz is fine).
insert image description here
Click the third icon in the lower left corner to quantify, click Targets in the menu bar, and the output will be a .coe file, which will be referenced when calling the fir IP core.
insert image description here

Guess you like

Origin blog.csdn.net/dovings/article/details/106888876
Recommended