When FPGA FIR filter, is the most commonly used direct-type structure, easy, when direct type structure, the structure can select the serial / parallel structure / distributed structure.
Multiply-accumulate operations in parallel FIR filter structure is implemented in parallel, the faster data processing speed, a plurality of multipliers simultaneously calculate the multiplication operation, the input data rate can be achieved in a processing clock rate of the system, and regardless of the order;
a talk on (5) Verilog serial filters
(3) Matlab simulation the FIR filter combined with Vivado
1. Create a new project and file
(1) New Verilog file
input 16-bit, output signal of the 16-bit, low-level reset reset rst_n;
(2) obtaining the filter coefficients h0 ~ h7;
according to a first talk by the FIR filter design fdatool toolbox of matlab is a way to use matlab design FIR low-pass filter is set to 8-bit quantization coefficient, (input rate can be achieved when parallel processing system clock rate) sampling clock 32 MHz, the cutoff frequency is set to 1 .5 MHz, the previous call IP core when the same (32 MHz clock, 0.5MHz + 5 MHz frequency noise signal, step 99);
amplitude-frequency characteristic curve of the upper right was observed, it was found the effect of the filter 7 does not order, at 5 MHz amplitude decays small, noise change here 13 MHz, the attenuation of the frequencies is large, the filtering effect is obvious;
derived parameters may be quantized directly derived .coe backup file, matlab will automatically open the file after export factor, in Verilog defining parameters constant language h0 ~ h7 (note that there is a specified number of symbols); (3)
a weighted sum filter
output of the FIR filter is the number of delay stages of the different input signals And convolution filter coefficients (multiply-accumulate operation, do first plurality of sets of multiplication, and then add up the multiplication accumulation), but also delay data corresponding to each input have different weights, and the weighted;
in accordance with the above structure block diagram, 8 multiplications do first, then added to the product of the multiplication;
2. matlab generate simulation signal
参数：抽样频率 Fs = 32 MHz，信号 f1 = 0.5 MHz，信号 f2 = 13 MHz，具体参见 第三讲 Matlab 与 Vivado 联合仿真 FIR 滤波器 ；
3. 编写仿真文件testbench
（1）例化模块；
（2）写 initial 块，初始化时钟、复位等；
（3）写 always 块，给出时钟翻转等；
（4）读写 .txt 文件，将 matlab 写好的 .txt 的数据赋给输入，把输出数据写入 .txt 文件给 matlab 分析；
具体见 第三讲 Matlab 与 Vivado 联合仿真 FIR 滤波器 ；
4. 仿真
（1）Verilog 仿真
可以看到，高频噪声基本被滤除，但是肉眼能观察出波形与标准正弦波有一定差距；
（2）Matlab仿真
Matlab仿真，分别是 f1、f2、f1+f2、滤波后的数据；
使用 matlab 做 FFT 进行频谱分析，使用 7 阶（8个系数）FIR 滤波器能够很好的保留低频 0.5 MHz 信号，滤除高频 13 MHz 信号；
（3）综合的 RTL 图
综合后共用到 6 个乘法器和 7 个加法器， Verilog 共计有 8 次乘法，但是其中有 2 个乘法的乘数是常数 0，所以 Vivado 只综合出 6 个乘法器；
与串行的对比，下图为串行 FIR 滤波器的 RTL 图：
5. 截位输出部分更改
还是看这张图，在对输入的 16-bit 数据做运算后，为了保证数据不溢出，得到的结果位宽逐渐变大，但是最后输出又是 16-bit，此时需要对数据进行截位（如果不截位，那么当一个数字信号处理系统较复杂的时候，数据的位宽会非常大，在处理中时不现实的），
当对本例中的 32-bit 的数据进行截位时，从哪里开始截取是一个经常会遇到的问题：
（1）截取高 16-bit (data_out_temp[31:16])，当数据比较大的时候可以这样做（高位上都是有效数据，用十进制举例 9*9 = 81，取十进制高位近似为 80，类比到二进制），这样相当于损失了一些低位的精度；
（2）截取低 16-bit (data_out_temp[15:0]) ，当数据比较小的时候可以（高位上没有有效数据，用十进制举例 2 * 2 = 4，取十进制低位为 4）；
（3）根据仿真出来的数据的表示范围，去掉高位的符号位，截取实际需要的数据；
需要对 data_out_temp[31:0] 截位（先截高 16 位作为 data_out 看波形），所以在仿真中先把该信号添加到波形显示窗口，该信号是一个内部信号，没有在输出端口，按照下图找到 testbench 仿真例化的器件，找到下方的 data_out_temp 信号并右键 Add to Wave Window（箭头1），点击 Restart（箭头2）之后再仿真 Run（箭头3），调成模拟波形 Analog（具体参见 Matlab 与 Vivado 联合仿真 FIR 滤波器）；
According to the arrow shown in expanded signal can be seen 23 ~ 31 bit data_out_temp are the same signal, representing the sign bit, 0 represents a positive number, 1 for negative, in fact, only one can be positive or negative sign represents , can take data_out_temp [23: 8] this 16-bit;
selected data_out_temp [23: 8] this 16-bit right after the new virtual bus (new virtual bus), Similarly, the data_out_temp [22: 7] also newly constructed virtual bus ( new Virtual Bus 1);
see, data_out_temp [23: 8] waveforms were not affected, data_out_temp [23: 8] waveforms can not reflect characteristics of data_out_temp, can be taken data_out_temp [23: 8] as the data_out;
assign data_out = data_out_temp[23:8];
Below, using data_out_temp [23: 8] as the data_out after, at the time the filter output value is the yellow line 16619, and the input signal at a magnitude data_in, and less than data_in, because the high frequency noise is filtered out above, this result in line with the actual situation;
the reasons here waveform if not also to deal with the problem may be related to the number of signed
Verilog study notes - signed number of multiplications and additions
