Original: https://www.zhihu.com/tardis/bd/art/426050677?source_id=1001
I read which article before, and I feel that I am not familiar with these few, but I usually use Feiqi, hahaha.
Memory devices (latches, flip-flops, registers)
1: RS latch
The feedback circuit is composed of two NOR gates or NAND gates
R and S are the set terminal and the reset terminal respectively, and the output Q reaches a stable state of 0 or 1
However, NOR latches should avoid 11, and NAND latches should avoid 00. In these two states, the next state will be uncertain. (Metastable)
At any moment, a change in the input will immediately cause a change in the output, that is, a level-sensitive latch . Therefore, its anti-drying performance is poor.
2: Level-triggered latch
Add the input control gate and CLK clock input signal on the basis of the basic RS latch.
2.1: SR latch for input signal to be enabled
The clock signal is used as enable (gate control), and the enable signal determines whether S and R affect the circuit. When the latch is in the enabled state, the output of the transparent latch will change with the change of the data input . If the enable is 0, the input of the sr latch will always be maintained.
During the period when it is enabled as 1, Q can be flipped several times with the change of RS.
2.2: D-Latch
RS is always inverted to form a level-triggered D flip-flop
The D latch ensures that no unstable conditions will occur.
3: Pulse-triggered trigger
Flip-flops are edge-sensitive memory elements. The action of data storage is synchronized by the rising or falling edge of a signal , which is usually a clock signal.
3.1 Master-slave RS flip-flop
When CLK is 1, the master flip-flop flips according to the value of RS, and the slave flip-flop keeps the state
When the falling edge of CLK arrives, the master flip-flop remains, and the slave flip-flop flips according to the output of the master flip-flop.
Therefore, in one clock cycle, the output state only flips once when the falling edge arrives.
Note: It is still necessary to pay attention to the constraints when both are 1.
3.2 Primary and secondary JK flip-flops
J is 0, K is 0, Q output keeps the original state;
J is 1, K is 0, and Q output is 1;
J is 0, K is 1, and Q output is 1;
J is 1, K is 1, Q output is deflected;
In one clock cycle, the output state is toggled only once when the falling edge arrives.
4: Edge-triggered flip-flop
4.1: D flip-flop
Using the D flip-flop starting from the falling edge, in the CMOS process, it is usually implemented by a transmission gate, which has fewer input signals and simple circuit design, so it is widely used.
4.2: T flip-flop
When the T flip-flop judges that the input signal T is valid on the rising edge of CLK, it will reverse the output itself, otherwise the output will remain. Typically used to implement counters.
5: Master-slave circuit structure with edge trigger function and additional clear signal Clear_bar
When the clearing signal Clear_bar is 0, the output of Q is invalid, the master transmission gate is in an active state when the clock is low, and the slave transmission gate is in an active state when the clock is high. When the clock is low, the output of the transfer gate is determined by Data, and when the clock is high, the output of the master transfer gate is passed to the slave transfer gate.
Summarize:
- 1. The output of the latch is only related to the input signal, and there is no clock terminal ; the flip-flop is controlled by the clock , and only when the clock is triggered, the sampling is collected and the output is generated.
2. The latch is controlled by the level and is controlled asynchronously ; the flip-flop is triggered by the clock edge and is controlled synchronously .
3. Latches are sensitive to clocks and are greatly affected by layout and wiring, and are prone to glitch signals; flip-flops are less affected by layout and wiring, and are less likely to generate glitch signals.
4. A latch requires fewer gate circuits than a flip-flop, so less resources are required.
Latches should be avoided in most designs.