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Two states of a sequential machine are said to be equivalent if they have the same output sequence (and the same next state) for all possible input sequences. The equivalent states of a sequential machine cannot be distinguished by observing the similarities and differences of the output sequences; merging equivalent states will not change the input and output characteristics of the state machine. Merging equivalent states by identifying them also does not change the input-output characteristics of the state machine. The state tables and state transition diagrams of sequential machines can be simplified by identifying and merging equivalent states, and the hardware overhead can be reduced without comprehensive consideration of circuit functions (because there is no need to encode equivalent states). Generally speaking, for each finite state machine, there will be at least one unique simplest equivalent state machine.
Example state table The state machine shown in Table 1 has two equivalent states: S_4 and S_5. Under the action of the input signal, the two states S_4 and S_5 have the same next state and output. That is to say, when the state machine is in state S_4 and has an input sequence, its output is exactly the same as when the state machine is in S_5 and is under the same input sequence. Figure 1 shows the state transition diagram of this state machine and illustrates how state S_4 and state S_5 map to the same next state; and for all valid inputs, these two equivalent states have the same output.
Table 1 Next state table and output table of equivalent state S_4 and S_5.
Replace S_5 with S_4 and delete the row where S_5 is located to simplify the table
| next state | output | |||
| enter | enter | |||
| current status | 0 | 1 | 0 | 1 |
| S_0 | S_6 | S_3 | 0 | 0 |
| S_1 | S_1 | S_6 | 0 | 1 |
| S_2 | S_2 | S_5 (S_4 should be used instead) | 0 | 1 |
| S_3 | S_7 | S_3 | 0 | 1 |
| S_4 | S_7 | S_2 | 0 | 0 |
| S_5 (delete this line) | S_7 | S_2 | 0 | 0 |
| S_6 | S_0 | S_1 | 0 | 0 |
| S_7 | S_4 | S_3 | 0 | 0 |
Figure 1 State transition diagram of equivalent state
Two states are said to be equivalent if the rows associated with them in the state table of the sequential machine are the same. The state transition diagram is simplified by deleting all but one equivalent state and redirecting the affected arc to the last retained hierarchical state. However, it should be noted that when the corresponding rows of two states in the state table are different, do not easily conclude that the two states are not equivalent states. The condition for the exact same row in the next state table is only its corresponding state, etc. A sufficient condition for price, not a necessary condition. Therefore, merely comparing rows in the state table is not a sufficient method to identify equivalent states, there are other equivalent states that this method may not detect.
A more general approach to removing equivalence states relies on the following recursive definition of equivalence: if two states have the same output for each input value, and for the same input value, the next state they transition to is also the same (or equal valence), then the two states are equivalent. The steps to delete the equivalent state can be summarized as follows: (1) draw a triangular table (see Table 2) to represent the possible combination pairs of different states; (2) analyze the equivalence conditions of the combined state Know that S_4 and S_5 are equivalent, so S_5 is no longer considered here). Looking at another example, if the next state that S_0 and S_4 transfer to is equivalent, and their corresponding outputs for each possible input are also the same, then S_0 and S_4 are considered to be equivalent states. In the state table shown in Figure 1, S_0 and S_4 have the same output, but only when the two conditions of S_6 and S_7 are equivalent and S_2 and S_3 are equivalent, S_0 and S_4 are equivalent.
Table 2 A table representing possible equivalence state pairs
| S_1 | impossible | |||||
| S_2 | impossible | S_6 and S_4 | ||||
| S_3 | impossible | S_1 and S_7, S_6 and S_3 | S_2 and S_7, S_4 and S_3 | |||
| S_4 | S_6 and S_7, S_3 and S_2 | impossible | impossible | impossible | ||
| S_6 | S_3 and S_1 | impossible | impossible | impossible | S_7 and S_0, S_2 and S_1 | |
| S_7 | S_6 and S_4 | impossible | impossible | impossible | S_2 and S_3 | S_0 and S_4, S_1 and S_3 |
| S_0 | S_1 | S_2 | S_3 | S_4 | S_6 |
In the corresponding row and column of the table, the equivalent conditions of a pair of states corresponding to the row and column are listed. For example, when the state machine is in state S_1, if the input is 0 or 1, its next state is respectively S_1 or S_6; similarly, when the state machine is in S_3, under the action of the above-mentioned same input, its next state is respectively S_7 and S_3. Therefore, the necessary and sufficient conditions for the equivalence of S_1 and S_3 are: S_1 and S_7 are equivalent, and S_6 and S_3 are equivalent (of course, if they have the same output at the same time, if this is violated, it will be marked as impossible).
In all possible equivalence states, we can find from the table that S_1 and S_3 are not equivalent, because S_1 and S_7 are marked as impossible to be equivalent in the table, and S_2 and S_3 are not equivalent, because S_2 and S_7 are in Equivalence is marked as impossible in the table. When discussing the equivalence relationship between S_7 and S_0, we will encounter some problems. The equivalence of S_7 and S_0 requires the equivalence of S_6 and S_4, the equivalence of S_6 and S_4 requires the equivalence of S_7 and S_0, S_2 and S_1, and the equivalence of S_2 and The equivalence of S_1 requires the equivalence of S_6 and S_4, and we will find that there are many circular equivalences, that is, A can prove B, and B can prove A, which does not determine whether A and B are true. But our principle is, if there is no contradiction, accept it. If we think that S_7 is equivalent to S_0, S_6 and S_4, and S_2 and S_1 respectively, and this will not produce contradictions, and can be logically self-consistent, then do so, because this can reduce the number of states of the state machine.
Finally, the simplified state transition diagram shown in Figure 2 can be obtained, which only includes 4 states instead of 8.
Figure 2 Completely simplified state transition diagram
The above content comes from "Verilog HDL Advanced Digital Design"