Perpetual calendar automatic digital calendar design verilog code based on ego1 development board

Name: Perpetual calendar automatic digital calendar design verilog code based on ego1 development board

Software: VIVADO

Language: Verilog

Code function:

Automatic digital calendar design 

Design an automatic digital calendar that uses a seven-segment digital display to display the year (last two digits), month, day and week number. Under the action of the day counting pulse, it automatically completes the counting and display of the month, day and week from January to December.

FPGA code Verilog/VHDL code resource download: www.hdlcode.com

This code has been verified on the ego1 development board. The development board is as follows. Other development boards can modify the pin adaptation:

Code download:Perpetual calendar automatic digital calendar design based on ego1 development board verilog codeName: Perpetual calendar automatic digital calendar design based on ego1 development board Verilog code (download the code at the end of the article) Software: VIVADO Language: Verilog code Function: Automatic digital calendar design Design automatic digital calendar, using a seven-segment digital display to display the year (last 2 digits), month, day and week number, counting the day pulse Under the function of the function, the counting and display of months, days and weeks from January to December are automatically completed. FPGA code Verilog/VHDL code resource download: www.hdlcode.com This code has been verified on the ego1 development board, development boardhttp://www.hdlcode.com/index.php?m= home&c=View&a=index&aid=305

1. Project documents

2. Program files

3. Program compilation

4. RTL diagram

5. Pin assignment

6. Testbench

7. Simulation diagram

Part of the code display:

//Top-level module
module calendar(
input clk_in,//clock
input rst,//reset
input switch,//switch
output  [7:0] dig_led_1,
output  [3:0] wei_led_1,
output  [7:0] dig_led_2,
output  [3:0] wei_led_2
);
wire day_add;
wire [7:0] year;//year
wire [7:0] month;//month
wire [7:0] day;//day
wire [3:0] week;
//Frequency division module
clk_div i_clk_div(
. clk_in(clk_in),//100M
.switch(switch),//switch
.day_add(day_add)//1Hz daily pulse
);
//Date control
data_ctrl i_data_ctrl
(
. clk_in(clk_in),//time
. rst(rst),//reset
.day_add(day_add),//Enable day counting
.  year(year),//年
.  month(month),//月
. day(day)//day
);
//week control
week_ctrl i_week_ctrl
(
. clk_in(clk_in),//time
. rst(rst),//reset
.day_add(day_add),//Enable day counting
.week(week)//week
);
   
   
//display module
display_num i_display_num(
. clk(clk_in),
.  year(year),//年
.  month(month),//月
. day(day),//day
.week(week),//week
. you_led_1(you_led_1),
. wei_led_1(wei_led_1),
. you_led_2(you_led_2),
. wei_led_2(wei_led_2)
);
endmodule