1. The word length of a computer is 32 bits and its storage capacity is 256MB. If the address is single-word, its addressing range is (D).
A 0—64MB B 0—32MB C 0—32M D 0—64M
Analysis: The addressing range of addressing by word is 0 ~ 64M. That is, the
calculation steps of 0000000~3FFFFFFH : 256M bytes = 256 * 1024 * 1024 * 8 bits,
addressing according to a single word of 32 bits. The number of bits of a single word is 32 bits, and the range is (256 * 1024 * 1024 * 8 bits)/32 bits = 64M for
addressing in 32-bit half-word length. The number of halfwords is 16 bits, and the range is (256 * 1024 * 1024 * 8 bits)/16 bits = 128M
32-bit double word addressing. The number of double words is 64 bits, and the range is (256 * 1024 * 1024 * 8 bits)/64 bits = 32M
2. Synchronous control is (C).
A Only suitable for CPU control method
B Only suitable for peripheral device control method
C Controlled by a unified timing signal method
D All instruction execution time is the same method
3. The sentence that describes the basic concepts in the PCI bus is incorrect (CD).
A PCI bus is a high-speed peripheral device that has nothing to do with the processor.
B The basic transmission mechanism of PCI bus is burst transmission.
C PCI device must be the master device.
D Only one PCI bus is allowed in the system.
4. In order to facilitate the realization of multi-level interrupts, the most effective way to save on-site information is to use (B).
A General register B Stack C Memory D External storage
5. Virtual storage technology mainly solves the (B) problem of storage.
A. Speed B. Expand storage capacity. C. Cost D. Take care of the first three
6. Knowing that x=-001111, y=+011001, find:
① [x] complement, [-x] complement, [y] complement, [-y] complement;
② x+y, xy, judge addition and subtraction Whether it overflows.
[x]original=100111 [x]complement=1110001 [-x]complement=0001111
[y]original=0011001 [y]complement=0011001 [-y]complement=1100111
X+y=0001010 xy=1011000
7. A certain DRAM chip has a storage capacity of 512×8 bits, and the number of address lines and data lines of the chip is (D).
A 8, 512 B 512, 8 C 18, 8 D 19, 8
8. In register indirect addressing mode, the operand is in (B).
A General register B Main memory unit C Program counter D Stack
9. The relationship between machine instructions and micro instructions is (A).
A Use several microinstructions to implement a machine instruction
B Use several machine instructions to implement a microinstruction
C Use one microinstruction to implement a machine instruction
D Use one machine instruction to implement a microinstruction
10. In centralized bus arbitration, the (A) method is the most sensitive to circuit failure.
A Daisy chain B Independent request C Counter timing query
11. The control-related reason in the pipeline is caused by the execution of the (A) instruction.
A conditional transfer B visits within C is logic D unconditional transfer
12. The PCI bus is a high-bandwidth and processor-independent standard bus. What is incorrect in the following description is (B).
A adopts synchronous timing protocol B adopts distributed arbitration strategy
C has automatic configuration capability D is suitable for low-cost small systems
13. In the following statement, what is not part of the three basic components of peripheral equipment is (D).
A Storage medium B Drive device C Control circuit D Counter
14. During interrupt processing, item (B) is completed by hardware.
A Close interrupt B Open interrupt C Save CPU scene D Restore CPU scene
15. IEEE1394 is a high-speed serial I/O standard interface. Among the following options, item (D) does not belong to the IEEE1394 protocol set.
A Business layer B Link layer C Physical layer D Serial bus management
16. Suppose the memory capacity is 128M words, the word length is 64 bits, and the number of modules is m=8, which are organized in sequential and interleaved modes respectively. The storage period T=200ns, the data bus width is 64 bits, and the bus transfer period τ=50ns. What is the bandwidth of sequential memory and interleaved memory?
17. There are two floating-point numbers N1=2j1×S1, N2=2j2×S2, where the order code is represented by a 4-shift code and the mantissa is represented by an 8-bit original code (including a sign bit). Suppose j1=(11)2, S1=(+0.0110011)2, j2=(-10)2, S2=(+0.1101101)2, find N1+N2, write the operation steps and results.
Solution: (1) Floating point multiplication rule:
N1 × N2 = (2j1 × S1) × (2j2 × S2) = 2 (j1 + j2) × (S1 × S2)
(2) Code summation:
j1 + j2 = 0
(3) Multiplying the mantissa: The
multiplicand S1 = 0.1001, the multiplier S2 = 0.1011, the absolute value of the product is multiplied by the absolute value of the mantissa, and the sign bit of the product =
0⊕0 = 0. According to the unsigned matrix multiplier operation: N1 × N2 = 20 × 0.01100011
(4) Mantissa normalization, rounding (four digits of mantissa)
N1 × N2 = (+ 0.01100011) 2 = (+0.1100) 2 × 2 (- 01) 2
18. The word length of a certain MCU is 32 bits, and its storage capacity is 4MB. If addressing by word, its addressing range is (A).
A 1M B 4MB C 4M D 1MB
analysis: addressing range according to word addressing
Calculation steps: 256M bytes = 256 * 1024 * 1024 * 8 bits,
according to computer according to 32-bit word length single word addressing. The number of single words is 32 bits, and the range is (4 * 1024 * 1024 * 8 bits)/32 bits = 1M.
Computers are addressed according to a 32-bit word length and a half word. The number of half-words is 16 bits, and the range is 2M
computers with 32-bit word length double-word addressing. The number of double words is 64 bits and the range is 0.5M
(1M=2^20)
19. In order to determine the address of the next microinstruction, the predicate method is usually adopted, and the basic idea is (C).
A Use the program counter PC to generate the subsequent micro-instruction address
B Use the micro-program counter µPC to generate the subsequent micro-instruction address
C Use the micro-instruction sequence control field to be specified by the designer or to generate the subsequent micro-instruction address
D through Specify a special field in the instruction to control the generation of subsequent microinstruction addresses
20. The register that tracks the address of the instruction subsequent in the CPU is (B).
A Address register B Program counter C Instruction register D General purpose register
21. The value in a certain register is the instruction code, and only the CPU (A) can identify it.
A Instruction decoder B Judgment program C Micro instruction D Timing signal
22. When using the DMA method to transmit data, each time a piece of data is transmitted, it takes one (C) time.
A instruction cycle B machine cycle C storage cycle D bus cycle
23. Compare the IEEE1394 serial standard interface with the SCSI parallel standard interface, and point out that the incorrect item in the following statement is (D).
A The former has a high data transmission rate.
B The former has good real-time data transmission.
C The former uses a 6-core cable and is small in size.
D The former does not have hot-plug capability
24. In the following statement, the problem item that does not belong to the virtual storage mechanism to be solved is (D).
A Scheduling problem
B Address mapping problem
C Replacement and update problem
D Expanding the storage capacity and word length of the physical main memory
25. The word length of a machine is 64 bits, one sign bit, and 63 bits represent the mantissa. If it is represented by a fixed-point integer, the maximum positive integer bit (A).
A +(263-1) B +(264-1) C -(263-1) D -(264-1)
26. Please select two sentences with correct descriptions (AC) from the descriptions in the floating point calculator below.
A Floating point arithmetic unit can be realized by two loosely connected fixed-point arithmetic components, first-order code and mantissa component.
The B-level code component can realize four operations of addition, subtraction, multiplication and division.
The C-order code component only performs order code addition, subtraction and comparison operations.
The D mantissa component only performs multiplication and division operations
27. The storage unit refers to (B).
A A storage element for storing 1 binary information bit
B A collection of all storage elements for 1 machine word
C A collection of all storage elements for 1 byte
D A collection of all storage elements for 2 bytes
28. The word length of a certain machine is 32 bits, and the storage capacity is 1MB. If addressing by word, its addressing range is (D).
A 0—1M B 0—512KB C 0—56K D 0—256KB
29. The addressing mode used to address the operand in a certain register is (C).
A direct B indirect C register direct D register indirect
30. The instruction function of the program control class is (D).
A Perform arithmetic operations and logic operations
B Perform data transfer between main memory and CPU
C Perform data transfer between CPU and I/O devices
D Change the order of program execution
31. The instruction cycle refers to (C).
A The time for the CPU to access an instruction from the host
B The time for the CPU to execute an instruction
C The time for the CPU to access an instruction from the host plus the execution of an instruction
D Clock cycle time
32. The sentence that describes the basic concepts in the contemporary popular bus structure is incorrect (AC).
A The current popular bus is not a standard bus.
B In the contemporary bus structure, the CPU and its private cache are connected to the bus as a module
C. One such CPU module is allowed in the system
33. The condition for an interrupt request is (B).
A An instruction execution ends
B An I/O operation ends
C A fault occurs inside the machine
D A DMA operation ends
34. The interrupt vector address is (B).
A Subroutine entry address
B Interrupt service routine entry address
C Interrupt service routine entry address indicator
D Routine entry address
35. IEEE1394 can realize real-time data transmission because of (AB).
A In addition to asynchronous transmission, it also provides synchronous transmission mode.
B Increases the clock frequency.
C In addition to priority arbitration, it also provides equal arbitration and emergency arbitration.
D Can be hot-plugged
36. The main advantage of direct mapping cache is simple to implement. The main disadvantage of this approach is (B).
A It is more expensive than other cache mapping methods.
B If two or more blocks in use are mapped to the same cache row, the hit rate will decrease.
C. Its access time is longer than other cache mapping methods.
D The number of blocks in the cache increases with The main memory capacity increases linearly
37. The characteristic of segment page storage management scheme in virtual storage is (D).
A Large waste of space, storage sharing is not easy, storage protection is easy, cannot be dynamically connected
B Space waste is small, storage sharing is easy, storage protection is not easy, cannot be dynamically connected
C Large waste of space, storage sharing is not easy, storage protection is easy, and
D space can be dynamically connected Little waste, easy storage sharing, easy storage protection, and dynamic connection
38. The single-word instruction of a certain machine is 32 bits, there are 40 instructions in total, 128 general-purpose registers, and the maximum addressing space of the main memory is 64M. There are six addressing modes: immediate addressing, direct addressing, register addressing, register indirect addressing, base value addressing, and relative addressing. Please design the instruction format and make necessary explanations.
39. Interleaved memory is essentially a multi-module memory, which performs multiple independent read and write operations in (A) mode.
A Pipeline B Resource repetition C Sequence D Resource sharing
40. What is the instruction cycle? CPU cycles? Clock cycle? What is the relationship between them?
The instruction cycle is the time required to execute an instruction. It is generally composed of several machine cycles. It is the entire time required from fetching the instruction, analyzing the instruction to executing it.
CPU cycle is also called machine cycle. It takes a long time for the CPU to access the memory once, so it is defined by the shortest time to read an instruction word from the memory. An instruction cycle is often composed of several CPU cycles. The
clock cycle is a fixed time interval defined by the CPU clock. It is the smallest unit of time for the CPU to work, also called the beat pulse or T cycle.
41. Compare the similarities and differences between cache and virtual storage.
Similarities: (1) The starting point is the same; both are hierarchical storage systems constructed to improve the performance-price ratio of storage systems. (2) The principle is the same; both use the principle of locality when the program is running to transfer the recently commonly used information blocks from a relatively slow and large-capacity memory to a relatively high-speed and small-capacity memory.
Differences: (1) Focus Different; cache mainly solves the problem of speed difference between main memory and CPU; virtual memory mainly solves the problem of storage capacity. (2) The data path is different; there is a direct path between the CPU and the cache and the main memory; while the virtual memory depends on the auxiliary memory, there is no direct path between it and the CPU. (3) Transparency is different; cache is transparent to system programmers and application programmers; while virtual storage is only transparent to application programmers. (4) The loss when it is not named is different; the performance loss of the system when the main memory is missed is much greater than the loss when the cache is missed.