homework 5
Number of questions: 21 Full marks: 100 Answer time: 03-23 09:45 to 03-29 23:59 91.7 points
1. Multiple choice questions (11 questions in total, 35 points)
1. (Single-choice question, 3 points) The main purpose of the hierarchical storage system for computer memory is to ________.
- A. Easy to read and write data
- B. Ease of system upgrade
- C. Solve the contradiction between storage capacity, price and access speed
- D. Reduce the size of the chassis
2. (Multiple choice, 3 points) The total time required for a complete read and write operation of the memory is called ________.
- A. Machine cycle
- B. Access cycle
- C. CPU cycles
- D. Access time
3. (Single-choice question, 3 points) The main memory space where user programs are stored belongs to ________.
- A. Direct Access Memory
- B. Random Access Memory
- C. Sequential Access Memory
- D. read-only memory
My answer: B: random access memory; correct answer: B: random access memory;
3 points
4. (Multiple choice, 3 points) The memory system in the computer system refers to ________.
- A. Main memory
- B. cache, main memory, and external memory
- C. RAM memory
- D. ROM memory
My answer: B: cache, main memory and external memory; correct answer: B: cache, main memory and external memory;
3 points
5. (Single-choice question, 3 points) A certain SRAM chip has a storage capacity of 64K×16 bits, and the number of address lines and data lines of the chip is ________
- A. 64,8
- B. 64,16
- C. 16,16
- D. 16,64
My answer: C:16,16; Correct answer: C:16,16;
3 points
6. (Single-choice question, 3 points) The word length of a certain computer is 32 bits, and its storage capacity is 4GB. If it is addressed by double word, its address range is ________.
- A. 8G
- B. 2G
- C. 4G
- D. 0.5G
My answer: D:0.5G; Correct answer: D:0.5G;
3 points
Answer analysis:
4GB
The word length is 32 bits, double word addressing, one address stores the number of bytes 32*2/8=8
Number of total addresses 4G/8=0.5G
7. (Multiple choice, 3 points) The following statement is correct ________.
- A. Semiconductor RAM is volatile RAM, and the information in static RAM is not easy to lose
- B. Semiconductor RAM is volatile RAM, while static RAM will not lose information only when the power is not lost
- C. Semiconductor RAM information is readable and writable, and can be maintained after power off
- D. All three are wrong
My answer: B: Semiconductor RAM is volatile RAM, while static RAM will not lose information only when power is not lost; correct answer: B: Semiconductor RAM is volatile RAM, while static RAM is only when power is not lost information is not lost;
3 points
8. (Single-choice question, 3 points) The storage unit refers to ( ).
- A. Storage element storing 1 bit of binary information
- B. A collection of all storage elements that store a machine word
- C. A collection of all storage elements that store 1 byte
- D. A collection of all storage elements that store 2 bytes
My answer: B: All the storage element collections storing 1 machine word; Correct answer: B: All storage element collections storing 1 machine word;
3 points
9. (Single-choice question, 3 points) A certain DRAM chip has a storage capacity of 512×8 bits. The number of address lines and data lines of the chip is ( ).
- A. 8,512
- B. 512,8
- C. 18,8
- D. 9,8
My answer: C:18,8; Correct answer: D:9,8;
0 points
10. (Single-choice question, 3 points) A computer has a word length of 32 bits and a storage capacity of 1MB. If it is addressed by word, its address range is ( ).
- A. 0-1M
- B. 0-512K
- C. 0-56K
- D. 0-256K
My answer: D:0-256K; Correct answer: D:0-256K;
3 points
11. (Single-choice question, 5 points) A certain SRAM chip has a capacity of 512×8 bits. Except for the power terminal and the ground terminal, the minimum number of lead wires of the chip should be ______.
- A. 23
- B. 25
- C. 50
- D. 19
My answer: D:19; Correct answer: D:19;
5 points
Answer analysis:
A certain SRAM chip has a capacity of 512×8 bits,
Data line 8, address line 9
It also includes at least 2 pieces: the connection line of the chip selection signal and the read and write signal.
2. Fill in the blanks (10 questions in total, 65 points)
12. (Fill in the blank, 4 points) SRAM relies on ____ to store information. DRAM stores information by ____.
my answer:
2 points
(1) Trigger
(2) capacitance
correct answer:
(1) Bistable flip-flop
(2) capacitance
13. (Fill in the blank, 4 points) If there are 1024 units in the RAM chip, and the single decoding method is used, the address decoder has ____ input lines, and the address decoder has ____ output lines.
my answer:
4 points
(1) 10
(2) 1024
correct answer:
(1) 10
(2) 1024
14. (Fill in the blank, 4 points) If there are 1024 units in the RAM chip, use double decoding, the address decoder has ____ input lines, and the address decoder has ____ output lines.
my answer:
4 points
(1) 10
(2) 64
correct answer:
(1) 10
(2) 64
Answer analysis:
1024=2^10 A total of 10 address lines are required,
5 input row decoders, 5 input column decoders
Row and column decoders each output 2^5=32 output lines
32+32=64
15. (Fill in the blank, 4 points)
The requirements for memory are large capacity, fast speed and low cost. In order to solve the contradictions in these three aspects, the computer adopts a multi-level storage architecture.
The tertiary storage system includes ____, ____, ____. (abbreviated for comparison)
my answer:
4 points
(1) cache
(2) main memory
(3) External storage
correct answer:
(1) cache
(2) main memory
(3) External storage
16. (Fill in the blank, 4 points) When the word length of a storage word is higher than 8 bits, there is a problem of the arrangement order of the multi-bytes inside the storage word, and the arrangement method is called endian mode. ______ (big-endian/little-endian) mode is to place the low-significant byte of a word on the low-address end of the memory, and the high-significant byte on the high-address end of the memory.
my answer:
4 points
(1) little endian
correct answer:
(1) little endian
17. (Fill in the blank, 5 points) There is a memory with a 20-bit address and a 32-bit word length, which can store ____(nKB/MB/GB) information.
Using the word storage method, the width of the address register in the CPU is ____, and the width of the data register is ____.
If the memory is composed of 512K×8-bit SRAM chips, ____ chips are required, and the organization method is ____ chips and 1 group, a total of ____ groups, and ____ bit addresses are required for chip selection.
For comparison, please enter Arabic numerals.
my answer:
5 points
(1) 4MB
(2) 20
(3) 32
(4) 8
(5) 4
(6) 2
(7) 1
18. (Fill in the blank, 5 points) If a 16M×64-bit memory module is composed of 4MX8-bit DRAM chips, it needs ____ chips, organization method, ____ chips in 1 group, ____ groups in total.
If the main memory of a 64-bit machine uses semiconductor memory, its address code is 26 bits, and the above-mentioned memory sticks can be inserted at most. If the sequential storage method is used, the common address lines of each memory bank are ____, A____~A0, and the addressing of the storage unit in the memory bank is completed. A25~A____ complete the selection of each memory stick through the 2-4 decoder.
my answer:
5 points
(1) 32
(2) 8
(3) 4
(4) 4
(5) 24
(6) 23
(7) 24
19. (Fill in the blank, 10 points) Use a 16K×8-bit DRAM chip to form a 64K×32-bit memory.
Please supplement the logical block diagram of the memory.
Chip extension:
4 chips and 1 group for bit extension, 4 groups for word extension,
the size of a single chip is ____(nKxm) (for the convenience of comparison, the multiplication can be written as the letter x).
(For the convenience of comparison, the lowest bit is the 0th bit, the highest bit is first, and English wavy lines are used in the middle)
Address line
The high bit address line____ (format such as: Am~An) selects the group through the 2-4 decoder.
The low-order address lines are shared by ____ to select the on-chip address.
Data line
The data line is 32 bits: ____ (format: Dm~Dn), which flows into the 4 chips in the group through branches, the
highest 8 bits are ____, and the lowest 8 bits are ____.
my answer:
correct answer:
(1) 16Kx8
(2) A15~A14
(3) A13~A0
(4) D31~D0
(5) D31~D24
(6) D7~D0
Answer analysis:
20. (Fill in the blank, 10 points) It is required to design a 1024K×32-bit memory with a 256K×16-bit SRAM chip. The SRAM chip has two control terminals: when CS is valid, the chip is selected. Perform a read operation when W#/R=1, and perform a write operation when W#/R=0.
Please supplement the logical block diagram of this memory.
Chip extension:
2 chips and 1 group for bit extension, 4 groups for word extension,
the size of a single chip is ____(nKxm) (for the convenience of comparison, just multiply and write the letter x).
(For the convenience of comparison, the lowest bit is the 0th bit, the highest bit is first, and English wavy lines are used in the middle)
Address line
High address line____ (format such as: Am~An) select which group by 2-4 decoder.
The low-order address lines are shared by ____ to select the on-chip address.
Data line
The data line is 32 bits: ____ (format such as: Dm~Dn), which flows into different chips in the group through branches,
the high bit is ____, and the low bit is ____.
correct answer:
(1) 256Kx16
(2) A19~A18
(3) A17~A0
(4) D31~D0
(5) D31~D16
(6) D15~D0
Answer analysis:
21. (Fill in the blank, 15 points)
In a machine, the memory consists of ROM and RAM chips.
The address space of the ROM area is the ROM area of 0000H~3FFFH.
The starting address of the RAM area is 6000H, the area size is 40K×16 bits, and it is composed of 8K×8 RAM chips.
Assuming that the address bus of the CPU is A15~A0, and the data bus is D15~D0, draw the logical block diagram of the memory.
The control signals are R/W (read/write), MREQ (memory access), and the RAM chip has CS and WE signal control terminals.
Please add the solution steps
Problem-solving steps:
1) Write the address 0000H~3FFFH of the ROM area into binary form
0000H, that is, 0000000000000000B
3FFFH, that is, ____B (16-digit binary number).
Accessing this area requires ____ address lines, and the size of the area is ____K
2) The RAM area is 40K×16 bits, a total of ____ pieces of 8K×8 RAM chips are required, and ____ pieces are in one group, a total of 5 groups.
The address of the 8K chip is 0~8K-1,
so the address range of each group of RAM chips: start address~start address+8K-1
8K-1 corresponds to 1 1111 1111 1111B (13 1s)
3) 40K RAM area, the address distribution starts from 6000H, and the addresses of the five 8K areas are
6000H~6000H+8K-1, 6000H+8K~6000H+8K+8K -1, ……………………
that is, 0110 0000 0000 0000B~ 0111 1111 1111 1111 (8K=2^13)
1000 0000 0000 0000B~1001 1111 1111 1111 1010 0000 0000
0000B ~1011 1111 1111 1111
1100 0000 0000 0000B~1101 1111 1111 1111
1110 0000 0000 0000B~1111 1111 1111 1111
4) The chip capacity is 8K, so the lower 13 bits of the address line are on-chip addresses,
A total of 16 address lines, the upper 3 address lines are used for chip selection.
The upper 3-bit address lines of the 5 areas are ____, ____, 101, 110, 111 respectively
5) Use A15~A13 as the chip selection signal, and select the RAM chip through the 3-8 decoder.
The upper 3 address bits of the ROM area are ____ and ____, so the 3-8 decoder outputs 0 and 1 when the ROM area is selected.
Because the output of the 3-8 decoder is active at low level, the chip selection signal is also active at low level.
That is, when either 0 or 1 of the 3-8 decoder outputs a low level, the ROM area is selected, so as shown in the figure, the ____ (and/or) gate is used to connect and serve as the ROM selection signal.
correct answer:
(1) 0011111111111111
(2) 14
(3) 16
(4) 10
(5) 2
(6) 011
(7) 100
(8) 000
(9) 001
(10) with