CPU instruction and tissue
Instruction set
basic concepts
After ① programmer with a variety of languages to be translated last (interpreted or compiled) into machine language expressed in the form of instructions to run on the computer. The computer instructions are microinstructions, machine instructions and macros points.A microprogram microinstruction level commands, a hardware; macro is composed by a number of machine instructions, belong to the software; machine instructions interposed therebetween, thus the hardware and software interface.
Set bits collectively machine instruction ② machine instructions a computer can perform.
Instruction format
The general format
| Opcode | address code |
|---|---|
| ON | D |
The number of addresses in instructions contained in the instruction is divided
. a three-address instruction: (Dl) the OP (D2 of) → D3
B two address instruction:. (Dl) the OP (D2 of) → D2 of
C single-address instruction:. (D) OP (A ) → A ( accumulator register)
D The zero-address instruction: No operation, downtime
Instruction length
Selection principle:
① memory instruction length should be an integer multiple of the basic word length.
② instruction word length should be as short as possible.
Addressing
① immediate addressing: | OP | operand address |
② direct addressing: | OP | @ indirect address |
③ indirect addressing: | OP | Rx | D |
④ indexed addressing: | OP | Rb | D |
⑤ based addressing:
⑥ relative addressing
⑦ implied addressing:
⑧ other addressing modes:
summary:
Instruction type
When designing a proprietary instruction set computer, several principles to be considered: the compatibility, completeness, uniformity, scalability.
Instruction type
When designing a proprietary instruction set computer, several principles to be considered: the compatibility, completeness, uniformity, scalability.
Stack and a stack access mode
（1）寄存器堆栈：由若干移位寄存器构成，采用下压式进栈方式。
（2）存储器堆栈：内存中开辟堆栈区，存储单元固定，而栈顶位置动态变化。在CPU中专门设置了堆栈指针SP，指示栈顶位置，存取只能在栈顶进行。
入栈操作：①SP-1→SP ②存入数据→（SP）
出栈操作：①（SP）内容读出 ②SP+1→SP
入栈操作：①SP+1→SP ②存入数据→（SP）
出栈操作：①（SP）内容读出 ②SP-1→SP
中央处理机组织
CPU的三种实现方式
CPU的三种实现方式：组合逻辑、PLA、微程序控制。
CPU中的主要寄存器
指令寄存器（IR）、程序计数器（PC）、地址寄存器（AR）、缓冲寄存器（DR）、累加寄存器（AC）、状态条件寄存器（PSW）
单总线数据通路
CPU四项基本功能
A.读取某一主存单元的内容，并将其装入某一个CPU寄存器;
（1） MAR←[R1] R1out, MARin
（2） Read Read
（3） WMFC WMFC
（4） R2←[MDR] MDRout,R2in
B.把一个数据字从某一CPU寄存器存入某个给定的主存单元;
(1) MAR←[R1] R1out, MARin
(2) MDR←[R2] R2out, MDRin
(3) Write Write
(4) WMFC WMFC
C.把一个数据字从某一CPU寄存器送到另一个寄存器或ALU;
R4 ←R1 R1out, R4in
D.进行一个算术运算或逻辑运算，将结果送入某一CPU寄存器。
(1)Y ←[R1]; R1out, Yin
(2)Z←[R2]+[Y]; R2out, Add, Zin
(3)R3 ←Z; Zout, R3in
CPU时序控制方式
（1）同步控制方式：同步控制方式的时序信号通常由周期、节拍和脉冲组成。指令的运行过程分为取指令、读取操作数及执行三个基本工作周期。
（2）异步控制方式
（3）联合控制方式
CPU控制流程
（1）取出指令
（2）分析指令
（3）执行指令
（4）对异常情况和某些请求的处理
一条完整指令的执行
①Add （R3），R1
This instruction is executed requires the following:
(1) instruction fetch;
(2) take the first operand (the content storage unit indicated by R3);
(3) Addition is performed;
(4) the result is stored in R1 .
| step | operating | Explanation |
|---|---|---|
| 1 | PCout,MARin, Read,Clear Y,1→C0，Add, Zin | Fetch, (PC) +1 |
| 2 | Salt, PCIN, WMFC | (PC)+1→PC |
| 3 | MDRout, | Instruction → IR |
| 4 | R3out,MARin,Read | Take data |
| 5 | R1out, Yin, WMFC | (R1) → Y |
| 6 | MDRout, Add, Zin | Adding |
| 7 | Salt, R1in, End | Results → R1 |
The control sequence of the unconditional jump instruction ②
| step | action |
|---|---|
| 1 | PCout, MARin, Read, Clear Y, 1 → C0, Add, Zin |
| 2 | Salt, PCIN, WMFC |
| 3 | MDRout, |
| 4 | PCout, Yin |
| 5 | (IR Offset field) out, Add, Zin |
| 6 | Salt, PCIN, End |
CPU performance design
CPU performance is the most important decision of three factors: the strength of the function, the length of the clock cycle instruction execution required number of clock cycles per instruction.
(1) multi-bus organization
(2) the instruction pipeline
(3) and the completion instruction issue policy
(4) Dynamic Execution
(5) a complete CPU
